![](http://datasheet.mmic.net.cn/120000/SH7709_datasheet_3575232/SH7709_258.png)
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When ordinary memories are connected, an RD signal that can be used as OE and the WE0–WE3
signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait
cycles using the A3W1 to A3W0 bits of WCR2.
When SDRAM is connected, the RAS3U, RAS3L signal, CAS signal, RD/WR signal, and byte
controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed.
For all of these, control of RAS3 , CAS , and data timing and of address multiplexing is set with
MCR.
Area 4: Area 4 physical addresses A28–A26 are 100. Addresses A31–A29 are ignored and the
address range is H'10000000 + H'20000000
× n – H'13FFFFFFF + H'20000000 × n (n = 0–6, n =
1–6 is the shadow space).
Only ordinary memories like SRAM and ROM can be connected to this space. Byte, word, or
longword can be selected as the bus width using the A4SZ1–A4SZ0 bits of BCR2. When the area
4 space is accessed, a CS4 signal is asserted. An RD signal that can be used as OE and the WE0–
WE3 signals for write control are also asserted. The number of bus cycles is selected between 0
and 10 wait cycles using the A4W2–A4W0 bits of WCR2.
Area 5: Area 5 physical addresses A28–A26 are 101. Addresses A31–A29 are ignored and the
address range is the 64 Mbytes at H'14000000 + H'20000000
× n – H'17FFFFFFF + H'20000000 ×
n (n
= 0–6, n = 1–6 is the shadow space).
Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be
connected to this space. PCMCIA interfaces only use their IC memory card interface, so the
address range becomes the 32 Mbytes at H'14000000 + H'20000000
× n – H'15FFFFFFF +
H'20000000
× n (n = 0–6, n = 1–6 is the shadow space).
For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width
using the A5SZ1–A5SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be
selected as the bus width using the A5SZ1–A5SZ0 bits of BCR2.
When the area 5 space is accessed and ordinary memory is connected, a CS5 signal is asserted. An
RD signal that can be used as OE and the WE0–WE3 signals for write control are also asserted.
When the PCMCIA interface is used, the CE1 signal, CE2 signal, OE signal, and WE signal are
asserted.
The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2–A5W0 bits of
WCR2. When a burst function is used, the bus cycle pitch of the burst cycle is determined within a
range of 2–10 according to the number of waits. When a PCMCIA interface is used the setup and
hold times of address CE1A and CE2A for the read/write strobe signals can be set in the range
0.5–3.5 using A5TED1–A5TED0 and A5TEH1–A5TEH0 bits of the PCR register.