![](http://datasheet.mmic.net.cn/120000/SH7709_datasheet_3575232/SH7709_501.png)
492
Bit 3: FER
Description
0
No receive framing error occurred in the data read from SCFRDR (initial value).
FER is cleared to 0 when the chip is power on reset or enters standby mode, or
when no framing error is present in the data read from SCFRDR.
1
A receive framing error occurred in the data read from SCFRDR.
FER is set to 1 when a framing error is present in the data read from SCFRDR.
Bit 2—Parity Error (PER): Indicates a parity error in the data read from the receive FIFO data
register (SCFRDR).
Bit 2: PER
Description
0
No receive parity error occurred in the data read from SCFRDR (initial value).
PER is cleared to 0 when the chip is power on reset or enters standby mode, or
when no parity error is present in the data read from SCFRDR.
1
A receive framing error occurred in the data read from SCFRDR.
PER is set to 1 when a parity error is present in the data read from SCFRDR.
Bit 1—Receive FIFO Data Full (RDF): Indicates that received data is transferred to the receive
FIFO data register (SCFRDR), the quantity of data in SCFRDR becomes more than the number of
receive triggers specified by the RTRG1 and RTRG0 bits in FIFO control register (SCFCR).
Bit 1: RDF
Description
0
The quantity of transmit data written to SCFRDR is less than the specified
number of receive triggers (initial value).
RDF is cleared to 0 at power onreset or at standby mode, or cleared when the
SCFRDR is read until the quantity of receive data in SCFRDR becomes less than
the specified number of receive triggers, when 1 is read from RDF, and 0 is then
written.
1
The quantity of receive data in SCFRDR is more than the specified number of
receive triggers.
RDF is set to 1 when the quantity of receive data which is greater than the
specified number of receive triggers is stored in SCFRDR. *1
Note:
Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data which can be
read when RDF is 1 is the specified number of receive triggers. If attempted to read
after all data in the SCFRDR have been read, the data is undefined. The quantity of
receive data in SCFRDR is indicated by the lower 8 bits of SCFTDR.
Bit 0—Receive Data Ready (DR): Indicates that the receive FIFO data register (SCFRDR) stores
the data which is less than the specified number of receive triggers, and that next data is not yet
received after 15 ETU has elapsed from the last stop bit.