409
Bit 4: FER
Description
0
Receiving is in progress or has ended normally (initial value). Clearing the RE
bit to 0 in the serial control register does not affect the FER bit, which retains
its previous value.
FER is cleared to 0 when the chip is reset or enters standby mode or software
reads FER after it has been set to 1, then writes 0 in FER.
1
A receive framing error occurred. When the stop bit length is two bits, only the
first bit is checked. The second stop bit is not checked. When a framing error
occurs, the SCI transfers the receive data into the SCRDR but does not set
RDRF. Serial receiving cannot continue while FER is set to 1. In the clock
synchronous mode, serial transmitting is also disabled.
FER is set to 1 if the stop bit at the end of receive data is checked and found
to be 0.
Bit 3—Parity Error (PER): Indicates that data reception (with parity) aborted due to a parity
error in the asynchronous mode.
Bit 3: PER
Description
0
Receiving is in progress or has ended normally (initial value). Clearing the RE
bit to 0 in the serial control register does not affect the PER bit, which retains
its previous value.
PER is cleared to 0 when the chip is reset or enters standby mode or software
reads PER after it has been set to 1, then writes 0 in PER.
1
A receive parity error occurred. When a parity error occurs, the SCI transfers
the receive data into the SCRDR but does not set RDRF. Serial receiving
cannot continue while PER is set to 1. In the clock synchronous mode, serial
transmitting is also disabled.
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the
serial mode register (SCSMR).
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the SCTDR did not contain valid data, so transmission has ended. TEND is a
read-only bit and cannot be written.
Bit 2: TEND
Description
0
Transmission is in progress.
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE, or data is written in SCTDR.
1
End of transmission (initial value).
TEND is set to 1 when the chip is reset or enters standby mode, TE is cleared
to 0 in the serial control register (SCSCR), or TDRE is 1 when the last bit of a
one-byte serial character is transmitted.