iv
6.3.4
Interrupt Control Register 2 (ICR2)..................................................................................... 124
6.3.5
PINT Interrupt Enable Register (PINTER)....................................................................... 125
6.3.6
Interrupt Request Register 0 (IRR0)................................................................................... 126
6.3.7
Interrupt Request Register 1 (IRR1)................................................................................... 129
6.3.8
Interrupt Request Register 2 (IRR2)................................................................................... 131
6.4
INTC Operation.............................................................................................................................................. 132
6.4.1
Interrupt Sequence ....................................................................................................................... 132
6.4.2
Multiple Interrupts........................................................................................................................ 134
6.5
Interrupt Response Time............................................................................................................................ 135
Section 7
User Break Controller (UBC)........................................................................................ 139
7.1
Overview ........................................................................................................................................................... 139
7.1.1
Features............................................................................................................................................. 139
7.1.2
Block Diagram............................................................................................................................... 140
7.1.3
Register Configuration ............................................................................................................... 141
7.1.4
Break Conditions and Register Settings............................................................................ 141
7.2
UBC Register Functions............................................................................................................................ 142
7.2.1
Break Address Register A (BARA)..................................................................................... 142
7.2.2
Break Address Register B (BARB)..................................................................................... 142
7.2.3
Break ASID Register A (BASRA)....................................................................................... 143
7.2.4
Break ASID Register B (BASRB)....................................................................................... 143
7.2.5
Break Address Mask Register A (BAMRA) ................................................................... 143
7.2.6
Break Address Mask Register B (BAMRB) ................................................................... 144
7.2.7
Break Bus Cycle Register A (BBRA) ............................................................................... 144
7.2.8
Break Bus Cycle Register B (BBRB)............................................................................... 145
7.2.9
Break Data Register B (BDRB) ........................................................................................... 146
7.2.10 Break Data Mask Register B (BDMRB).......................................................................... 147
7.2.11 Break Control Register (BRCR)........................................................................................... 148
7.3
UBC Operation............................................................................................................................................... 150
7.3.1
User Break Operation Flow ..................................................................................................... 150
7.3.2
Instruction Fetch Cycle Break ............................................................................................... 151
7.3.3
Data Access Cycle Break ........................................................................................................ 151
7.3.4
Saved Program Counter (PC) Value................................................................................... 152
7.3.5
Examples of Use ........................................................................................................................... 153
7.3.6
Cautions ............................................................................................................................................ 155
Section 8
Power-Down Modes............................................................................................................ 157
8.1
Overview ........................................................................................................................................................... 157
8.1.1
Power-Down Modes..................................................................................................................... 157
8.1.2
Pin Configuration.......................................................................................................................... 158