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9.7.1
Clock Modes 0–2.......................................................................................................................... 189
9.7.2
Clock Modes 3, 4 ......................................................................................................................... 189
9.8
Overview of the WDT................................................................................................................................. 189
9.8.1
Block Diagram of the WDT .................................................................................................... 189
9.8.2
Register Configurations ............................................................................................................. 190
9.9
WDT Registers............................................................................................................................................... 190
9.9.1
Watchdog Timer Counter (WTCNT).................................................................................. 190
9.9.2
Watchdog Timer Control/Status Register (WTCSR) ................................................. 191
9.9.3
Notes on Register Access......................................................................................................... 193
9.10
Using the WDT .............................................................................................................................................. 193
9.10.1 Canceling Standbys..................................................................................................................... 193
9.10.2 Changing the Frequency ........................................................................................................... 194
9.10.3 Using Watchdog Timer Mode ................................................................................................ 194
9.10.4 Using Interval Timer Mode...................................................................................................... 194
9.11
Notes on Board Design............................................................................................................................... 195
Section 10 Bus State Controller (BSC).............................................................................................. 197
10.1
Overview ........................................................................................................................................................... 197
10.1.1 Features............................................................................................................................................. 197
10.1.2 Block Diagram............................................................................................................................... 200
10.1.3 Pin Configuration.......................................................................................................................... 202
10.1.4 Register Configuration ............................................................................................................... 204
10.1.5 Area Overview ............................................................................................................................... 205
10.1.6 PCMCIA Support.......................................................................................................................... 208
10.2
BSC, BSCP Registers ................................................................................................................................ 212
10.2.1 Bus Control Register 1 (BCR1) ............................................................................................ 212
10.2.2 Bus Control Register 2 (BCR2) ............................................................................................ 215
10.2.3 Bus Control Register 3 (BCR3) ............................................................................................ 217
10.2.4 Wait State Control Register 1 (WCR1)............................................................................ 220
10.2.5 Wait State Control Register 2 (WCR2)............................................................................ 221
10.2.6 Individual Memory Control Register (MCR).................................................................. 224
10.2.7 DRAM Control Register (DCR)............................................................................................ 229
10.2.8 PCMCIA Control Register (PCR)........................................................................................ 232
10.2.9 SDRAM Mode Register (SDMR) ........................................................................................ 233
10.2.10 Refresh Timer Control/Status Register (RTCSR) ........................................................ 234
10.2.11 Refresh Timer Counter (RTCNT) ......................................................................................... 236
10.2.12 Refresh Time Constant Register (RTCOR)..................................................................... 237
10.2.13 Refresh Count Register (RFCR)........................................................................................... 237
10.2.14 Cautions on Accessing Refresh Control Related Registers ..................................... 238
10.3
BSC Operation ............................................................................................................................................... 239