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| 型号： | W9725G6KB-25I |
| 厂商： | Winbond Electronics |
| 文件页数： | 41/87页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 256MBIT 84WBGA |
| 标准包装： | 209 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 256M（16Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | * |
| 其它名称： | Q7118748 |
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W9725G6KB
Operating Burst Read Current
All banks open, Continuous burst reads, I OUT = 0 mA;
BL = 4, CL = CL (IDD), AL = 0;
I DD4R
t CK = t CK(IDD) ; t RAS = t RASmax(IDD) , t RP = t RP(IDD) ;
CKE is HIGH, CS is HIGH between valid commands;
125
105
95
mA
1,2,3,4,5,
6
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL (IDD), AL = 0;
I DD4W
t CK = t CK(IDD) ; t RAS = t RASmax(IDD) , t RP = t RP(IDD) ;
CKE is HIGH, CS is HIGH between valid commands;
130
110
100
mA
1,2,3,4,5,
6
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Burst Refresh Current
t CK = t CK(IDD) ;
I DD5B
Refresh command every t RFC(IDD) interval;
CKE is HIGH, CS is HIGH between valid commands;
75
70
65
mA
1,2,3,4,5,
6
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Self Refresh Current
I DD6
CKE ? ≤ 0.2 V, external clock off, CLK and CLK at 0 V;
Other control and address inputs are FLOATING;
6
6
6
mA
1,2,3,4,5,
6,7
Data bus inputs are FLOATING. (T CASE ≤ 85°C)
Operating Bank Interleave Read Current
All bank interleaving reads, I OUT = 0mA;
BL = 4, CL = CL (IDD), AL = t RCD(IDD) - 1 x t CK(IDD) ;
I DD7
t CK = t CK(IDD) , t RC = t RC(IDD) , t RRD = t RRD(IDD) , t FAW
= t FAW(IDD) , t RCD = t RCD(IDD) ;
160
135
115
mA
1,2,3,4,5,
6
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
Notes:
1.
2.
3.
4.
V DD = 1.8 V ? 0.1V; V DDQ = 1.8 V ? 0.1V.
I DD specifications are tested after the device is properly initialized.
Input slew rate is specified by AC Parametric Test Condition.
I DD parameters are specified with ODT disabled.
5. Data Bus consists of DQ, LDM, UDM, LDQS, LDQS , UDQS and UDQS .
6. Definitions for I DD
LOW = V in ≤ V IL (ac) (max)
HIGH = V in ≥ V IH (ac) (min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at V REF = V DDQ /2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
7. The following I DD values must be derated (I DD limits increase), when T CASE ≥ 85°C I DD2P must be derated by 20%;
I DD3P (slow) must be derated by 30% and I DD6 must be derated by 80%. (I DD6 will increase by this amount if T CASE < 85°C
and the 2X refresh option is still enabled)
Publication Release Date: Sep. 03, 2012
- 41 -
Revision A03
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G6KB25I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X16, IND TEMP |
| W9725G6KB25K | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G6KB-3 | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G8JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 8 BIT DDR2 SDRAM |
| W9725G8JB25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 32Mx8 1.8V 60-Pin WBGA |
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