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| 型号： | W9725G6KB-25I |
| 厂商： | Winbond Electronics |
| 文件页数： | 60/87页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 256MBIT 84WBGA |
| 标准包装： | 209 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 256M（16Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | * |
| 其它名称： | Q7118748 |
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W9725G6KB
44. Data setup and hold time derating.
DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe
ΔtDS, ΔtDH Derating Values for DDR2-667, DDR2-800 and DDR2-1066 (All units in ?p S ?; the note applies to
DQ
Slew
Rate
the entire table)
DQS/ DQS Differential Slew Rate
(V/nS)
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
0.8 V/nS
ΔtDS ΔtD H ΔtDS ΔtD H ΔtDS ΔtD H ΔtDS ΔtD H ΔtDS ΔtD H ΔtDS ΔtD H ΔtDS ΔtD H ΔtDS ΔtD H ΔtDS ΔtD H
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
100
67
0
-
-
-
-
-
-
45
21
0
-
-
-
-
-
-
100
67
0
-5
-
-
-
-
-
45
21
0
-14
-
-
-
-
-
100
67
0
-5
-13
-
-
-
-
45
21
0
-14
-31
-
-
-
-
-
79
12
7
-1
-10
-
-
-
-
33
12
-2
-19
-42
-
-
-
-
-
24
19
11
2
-10
-
-
-
-
24
10
-7
-30
-59
-
-
-
-
-
31
23
14
2
-24
-
-
-
-
22
5
-18
-47
-89
-
-
-
-
-
35
26
14
-12
-52
-
-
-
-
17
-6
-35
-77
-140
-
-
-
-
-
38
26
0
-40
-
-
-
-
-
6
-23
-65
-128
-
-
-
-
-
-
38
12
-28
-
-
-
-
-
-
-11
-53
-116
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and
tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS .
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded ?VREF(dc) to AC region?, use nominal slew rate for derating value . See Figure 24 Illustration of nominal slew rate for
tDS (differential DQS, DQS ).
If the actual signal is later than the nominal slew rate line anywhere between shaded ?VREF(dc) to AC region?, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 25 Illustration of tangent line
for tDS (differential DQS, DQS ).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded ? DC level to VREF(dc) region?, use nominal slew rate for derating value . See Figure 26 Illustration of nominal slew rate
for tDH (differential DQS, DQS ).
If the actual signal is earlier than the nominal slew rate line anyw here between shaded ? DC to VREF(dc) region?, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 27 Illustration of
tangent line for tDH (differential DQS, DQS ).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential
data strobe table, the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Publication Release Date: Sep. 03, 2012
- 60 -
Revision A03
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| W9751G6KB-25 | IC DDR2 SDRAM 512MBIT 84WBGA |
| W9812G6JH-6I | IC SDRAM 128MBIT 54TSOPII |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G6KB25I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X16, IND TEMP |
| W9725G6KB25K | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G6KB-3 | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G8JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 8 BIT DDR2 SDRAM |
| W9725G8JB25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 32Mx8 1.8V 60-Pin WBGA |
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