参数资料
型号: W9725G6KB-25I
厂商: Winbond Electronics
文件页数: 46/87页
文件大小: 0K
描述: IC DDR2 SDRAM 256MBIT 84WBGA
标准包装: 209
格式 - 存储器: RAM
存储器类型: DDR2 SDRAM
存储容量: 256M(16Mx16)
速度: 2.5ns
接口: 并联
电源电压: 1.7 V ~ 1.9 V
工作温度: -40°C ~ 95°C
封装/外壳: 84-TFBGA
供应商设备封装: 84-WBGA(8x12.5)
包装: *
其它名称: Q7118748
W9725G6KB
AC Characteristics and Operating Condition for -25/25I/25A/25K/-3 speed grades, continued
Notes: 1-3 and 45-47 apply to the entire table
SYM.
SPEED GRADE
Bin(CL-t RCD -t RP)
DDR2-800
(-25/25I/25A/25K)
5-5-5/6-6-6
DDR2-667
(-3)
5-5-5
UNITS 25 NOTES
PARAMETER
MIN.
MAX.
MIN.
MAX.
t WPRE
Write preamble
0.35
?
0.35
?
t CK(avg)
t WPST
t RPRE
t RPST
Write postamble
Read preamble
Read postamble
0.4
0.9
0.4
0.6
1.1
0.6
0.4
0.9
0.4
0.6
1.1
0.6
t CK(avg)
t CK(avg)
t CK(avg)
12
14,36
14,37
t DS(base) DQ and DM input setup time
t DH(base) DQ and DM input hold time
50
125
?
?
100
175
?
?
pS
pS
16,27,29,
41,42,44
17,27,29,
41,42,44
t DS(ref)
t DH(ref)
t DIPW
t HZ
t LZ(DQS)
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width for each
input
Data-out high-impedance time from
CLK/ CLK
DQS/ DQS -low-impedance time from
250
250
0.35
?
t AC,min
?
?
?
t AC,max
t AC,max
300
300
0.35
?
t AC,min
?
?
?
t AC,max
t AC,max
pS
pS
t CK(avg)
pS
pS
16,27,29,
41,42,44
17,27,29,
41,42,44
15,35
15,35
CLK/ CLK
t LZ(DQ)
DQ low-impedance time from CLK/ CLK
2 x t AC,min
t AC,max
2 x t AC,min
t AC,max
pS
15,35
Min.
Min.
t HP
Clock half pulse width
(t CH(abs) ,
(t CH(abs) ,
pS
32
t CL(abs) )
t CL(abs) )
t QHS
t QH
t XSNR
t XSRD
t XP
t XARD
t XARDS
t AOND
t AON
t AONPD
t AOFD
t AOF
t AOFPD
t ANPD
Data hold skew factor
DQ/DQS output hold time from DQS
Exit Self Refresh to a non-Read command
Exit Self Refresh to a Read command
Exit precharge power down to any
command
Exit active power down to Read command
Exit active power down to Read command
(slow exit, lower power)
ODT turn-on delay
ODT turn-on
ODT turn-on (Power Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power Down mode)
ODT to power down Entry Latency
?
t HP - t QHS
t RFC + 10
200
2
2
8 - AL
2
t AC,min
t AC,min + 2
2.5
t AC,min
t AC,min + 2
3
300
?
?
?
?
?
?
2
t AC,max + 0.7
2 x t CK(avg) +
t AC,max + 1
2.5
t AC,max + 0.6
2.5 x t CK(avg)
+ t AC,max + 1
?
?
t HP - t QHS
t RFC + 10
200
2
2
7 - AL
2
t AC,min
t AC,min + 2
2.5
t AC,min
t AC,min + 2
3
340
?
?
?
?
?
?
2
t AC,max + 0.7
2 x t CK(avg) +
t AC,max + 1
2.5
t AC,max + 0.6
2.5 x t CK(avg)
+ t AC,max + 1
?
pS
pS
nS
n CK
n CK
n CK
n CK
n CK
nS
nS
n CK
nS
nS
n CK
33
34
23
18
18,19
20
20,35
21,39
21,38,39
t AXPD
ODT Power Down Exit Latency
8
8
n CK
t MRD
Mode Register Set command cycle time
2
?
2
?
n CK
t MOD
t OIT
t DELAY
MRS command to ODT update delay
OCD Drive mode output delay
Minimum time clocks remain ON after
CKE asynchronously drops LOW
0
0
t IS +t CK(avg) +
t IH
12
12
?
0
0
t IS +t CK(avg) +
t IH
12
12
?
nS
nS
nS
23
23
22
Publication Release Date: Sep. 03, 2012
- 46 -
Revision A03
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