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| 型号： | W9725G6KB-25I |
| 厂商： | Winbond Electronics |
| 文件页数： | 7/87页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 256MBIT 84WBGA |
| 标准包装： | 209 |
| 格式 - 存储器： | RAM |
| 存储器类型： | DDR2 SDRAM |
| 存储容量： | 256M（16Mx16） |
| 速度： | 2.5ns |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 84-TFBGA |
| 供应商设备封装： | 84-WBGA（8x12.5） |
| 包装： | * |
| 其它名称： | Q7118748 |
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W9725G6KB
6. BALL DESCRIPTION
BALL NUMBER
SYMBOL
FUNCTION
DESCRIPTION
Provide the row address for active commands, and the column address
M8,M3,M7,N2,N8,N3
,N7,P2,P8,P3,M2,P7
,R2
A0 ? A12
Address
and Auto-precharge bit for Read/Write commands to select one
location out of the memory array in the respective bank.
Row address: A0? A12.
Column address: A0?A8. (A10 is used for Auto -precharge)
L2,L3
G8,G2,H7,H3,H1,H9
,F1,F9,C8,C2,D7,D3,
D1,D9,B1,B9
K9
BA0 ? BA1
DQ0 ? DQ15
ODT
Bank Select
Data Input
/ Output
On Die
Termination
Control
BA0 ? BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Bi-directional data bus.
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM.
Data Strobe for Lower Byte: Output with read data, input with write data
for source synchronous operation. Edge-aligned with read data, center-
F7,E8
LDQS, LDQS LOW Data Strobe
aligned with write data. LDQS corresponds to the data on DQ0 ? DQ7.
LDQS is only used when differential data strobe mode is enabled via
the control bit at EMR (1)[A10 EMRS command].
Data Strobe for Upper Byte: Output with read data, input with write data
for source synchronous operation. Edge-aligned with read data, center-
B7,A8
UDQS, UDQS
UP Data Strobe
aligned with write data.
UDQS corresponds to the data on
DQ8 ? DQ15. UDQS is only used when differential data strobe mode is
enabled via the control bit at EMR (1)[A10 EMRS command].
All commands are masked when CS is registered HIGH . CS provides
L8
CS
Chip Select
for external bank selection on systems with multiple ranks. CS is
considered part of the command code.
K7,L7,K3
RAS , CAS ,
WE
Command Inputs
RAS , CAS and WE (along with CS ) define the command being
entered.
DM is an input mask signal for write data. Input data is masked when
B3,F3
UDM, LDM
Input Data Mask
DM is sampled high coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
CLK and CLK are differential clock inputs. All address and control
J8,K8
CLK, CLK
Differential Clock
Inputs
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
K2
CKE
Clock Enable
CKE (registered HIGH) activates and CKE (registered
deactivates clocking circuitry on the DDR2 SDRAM.
LOW)
J2
V REF
Reference Voltage V REF is reference voltage for inputs.
A1,E1,J9,M9,R1
A3,E3,J3,N1,P9
V DD
V SS
Power Supply
Ground
Power Supply: 1.8V ? 0.1V.
Ground.
A9,C1,C3,C7,C9,E9,
G1,G3,G7,G9
V DDQ
DQ Power Supply DQ Power Supply: 1.8V ? 0.1V.
A7,B2,B8,D2,D8,E7,
F2,F8,H2,H8
A2,E2,L1,R3,R7,R8
J7
V SSQ
NC
V SSDL
DQ Ground
No Connection
DLL Ground
DQ Ground. Isolated on the device for improved noise immunity.
No connection.
DLL Ground.
J1
V DDL
DLL Power Supply DLL Power Supply: 1.8V ? 0.1V.
Publication Release Date: Sep. 03, 2012
-7-
Revision A03
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W9725G6KB25I TR | 制造商:Winbond Electronics Corp 功能描述:256M DDR2-800, X16, IND TEMP |
| W9725G6KB25K | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G6KB-3 | 制造商:WINBOND 制造商全称:Winbond 功能描述:DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask |
| W9725G8JB | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M ? 4 BANKS ? 8 BIT DDR2 SDRAM |
| W9725G8JB25 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 32Mx8 1.8V 60-Pin WBGA |
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