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参数资料
型号： ADV7184BSTZ
厂商： Analog Devices Inc
文件页数： 103/112页
文件大小： 0K
描述： IC DECODER VID SDTV MULTI 80LQFP
标准包装： 1
类型： 视频解码器
应用： 投影仪，录音机，安全
电压 - 电源，模拟： 3.15 V ~ 3.45 V
电压 - 电源，数字： 1.65 V ~ 2 V
安装类型： 表面贴装
封装/外壳： 80-LQFP
供应商设备封装： 80-LQFP（14x14）
包装： 托盘
ADV7184
Rev. A | Page 90 of 112
Bit1
Address
Register
Bit Description
7 6 5 4 3 2 1 0 Comments
Notes
0x31
Reserved.
0 1 0 Set to default
Vsync Field
Control 1
0
Start of line relative to HSE
HSE = hsync end.
HVSTIM. This bit selects where within a line of
video the VS signal is asserted.
1
Start of line relative to HSB
HSB = hsync begin.
NEWAVMODE. Sets the EAV/SAV mode.
0
EAV/SAV codes generated to suit
ADI encoders
1
Manual VS/FIELD position
controlled by Registers 0x32, 0x33,
and 0xE5 to 0xEA
Reserved.
0 0 0
Set to default
0x32
Reserved.
0 0 0 0 0 1 Set to default
NEWAVMODE bit must be set high.
Vsync Field
Control 2
0
VS goes high in the middle of the
line (even field)
VSBHE.
1
VS changes state at the start of the
line (even field)
0
VS goes high in the middle of the
line (odd field)
VSBHO.
1
VS changes state at the start of the
line (odd field)
Reserved.
0 0 0 1 0 0 Set to default
0
VS goes low in the middle of the
line (even field)
VSEHE.
1
VS changes state at the start of the
line (even field)
0
VS goes low in the middle of the
line (odd field)
0x33
Vsync Field
Control 3
VSEHO.
1
VS changes state at the start of the
line (odd field)
NEWAVMODE bit must be set high.
HSE [10:8]. HS end. These bits allow the posi-
tioning of the HS output within the video line.
0 0 0 HS output ends HSE [10:0] pixels
after the falling edge of hsync
Using HSB and HSE, the user can
program the position and length of
the output hsync.
Reserved.
0
Set to 0
HSB [10:8]. HS begin. These bits allow the posi-
tioning of the HS output within the video line.
0 0 0
HS output starts HSB [10:0] pixels
after the falling edge of hsync
0x34
Hsync Position
Control 1
Reserved.
0
Set to 0
0x35
Hsync Position
Control 2
HSB [7:0]. Using HSB [10:0] and HSE [10:0]
(see Register 0x34), the user can program the
position and length of the HS output signal.
0 0 0 0 0 0 1 0
0x36
Hsync Position
Control 3
HSE [7:0]. See Registers 0x34 and 0x35.
0 0 0 0 0 0 0 0
0 Invert polarity
PCLK. Sets the polarity of LLC.
1 Normal polarity, as per the timing
diagrams (
Figure 2 to Figure
4)
Sets the polarity of LLC on both LLC1
and LLC2.
Reserved.
0 0
Set to 0
0
Active high
PF. Sets the FIELD polarity.
1
Active low
Reserved.
0
Set to 0
0
Active high
PVS. Sets the VS polarity.
1
Active low
Reserved.
0
Set to 0
0
Active high
0x37
Polarity
PHS. Sets the HS polarity.
1
Active low
0x38
NTSC Comb Control
0 0 0 Adaptive 3-line, 3-tap luma
1 0 0 Use low-pass notch
1 0 1 Fixed luma comb (two lines)
Top lines of memory.
1 1 0 Fixed luma comb (three lines)
All lines of memory.
YCMN [2:0]. Luma comb mode NTSC.
1 1 1 Fixed luma comb (two lines)
Bottom lines of memory.
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