参数资料
| 型号： | ADV7184BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/112页 |
| 文件大小： | 0K |
| 描述： | IC DECODER VID SDTV MULTI 80LQFP |
| 标准包装： | 1 |
| 类型： | 视频解码器 |
| 应用： | 投影仪，录音机，安全 |
| 电压 - 电源，模拟： | 3.15 V ~ 3.45 V |
| 电压 - 电源，数字： | 1.65 V ~ 2 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
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ADV7184
Rev. A | Page 103 of 112
Bit1
Address Register
Bit Description
7 6 5 4 3 2 1 0
Comments
Notes
0x4A
Interrupt Status 3
(Read Only)
0
No change in SD signal standard
detected at the output.
SD_OP_CHNG_Q. This bit indicates if the
SD 60 Hz or SD 50 Hz frame rate is at output.
1
A change in SD signal standard is
detected at the output.
0
No change in SD vertical sync lock
status.
SD_V_LOCK_CHNG_Q.
1
SD vertical sync lock status has
changed.
0
No change in SD horizontal sync
lock status.
SD_H_LOCK_CHNG_Q.
1
SD horizontal sync lock status has
changed.
0
No change in AD_RESULT [2:0] bits
in Status Register 1.
SD_AD_CHNG_Q. SD autodetect changed.
1
AD_RESULT [2:0] bits in Status
Register 1 have changed.
0
No change in SECAM lock status.
SCM_LOCK_CHNG_Q. SECAM lock.
1
SECAM lock status has changed.
0
No change in PAL swinging burst
lock status.
PAL_SW_LK_CHNG_Q.
1
PAL swinging burst lock status has
changed.
Reserved.
x
Not used.
Reserved.
x
Not used.
These bits can be cleared and
masked by Register 0x4B if no
change is detected and by
Register 0x4C if a change is
detected.
0
Do not clear.
SD_OP_CHNG_CLR.
1
Clears SD_OP_CHNG_Q bit.
0
Do not clear.
SD_V_LOCK_CHNG_CLR.
1
Clears SD_V_LOCK_CHNG_Q bit.
0
Do not clear.
SD_H_LOCK_CHNG_CLR.
1
Clears SD_H_LOCK_CHNG_Q bit.
0
Do not clear.
SD_AD_CHNG_CLR.
1
Clears SD_AD_CHNG_Q bit.
0
Do not clear.
SCM_LOCK_CHNG_CLR.
1
Clears SCM_LOCK_CHNG_Q bit.
0
Do not clear.
PAL_SW_LK_CHNG_CLR.
1
Clears PAL_SW_LK_CHNG_Q bit.
Reserved.
x
Not used.
0x4B
Interrupt Clear 3
(Write Only)
Reserved.
x
Not used.
0
Masks SD_OP_CHNG_Q bit.
SD_OP_CHNG_MSKB.
1
Unmasks SD_OP_CHNG_Q bit.
0
Masks SD_V_LOCK_CHNG_Q bit.
SD_V_LOCK_CHNG_MSKB.
1
Unmasks SD_V_LOCK_CHNG_Q bit.
0
Masks SD_H_LOCK_CHNG_Q bit.
SD_H_LOCK_CHNG_MSKB.
1
Unmasks SD_H_LOCK_CHNG_Q bit.
0
Masks SD_AD_CHNG_Q bit.
SD_AD_CHNG_MSKB.
1
Unmasks SD_AD_CHNG_Q bit.
0
Masks SCM_LOCK_CHNG_Q bit.
SCM_LOCK_CHNG_MSKB.
1
Unmasks SCM_LOCK_CHNG_Q bit.
0
Masks PAL_SW_LK_CHNG_Q bit.
PAL_SW_LK_CHNG_MSKB.
1
Unmasks PAL_SW_LK_CHNG_Q bit.
Reserved.
x
Not used.
0x4C
Interrupt Mask 3
(Read/Write)
Reserved.
x
Not used.
0x4E
0
Closed captioning not detected.
Interrupt Status 4
(Read Only)
VDP_CCAPD_Q.
1
Closed captioning detected.
Reserved.
x
0
CGMS/WSS data is not changed/not
available.
VDP_CGMS_WSS_CHNGD_Q. See Register
0x9C, Bit 4, of the user sub map to
determine whether an interrupt is issued for
a change in detected data or when data
is detected regardless of content.
1
CGMS/WSS data is changed/available.
These bits can be cleared by
Register 0x4F and masked by
Register 0x50.
Note that an interrupt in
Register 0x4E for the CC,
Gemstar, CGMS, WSS, VPS,
PDC, UTC, and VITC data can
be initiated by using the VDP
data slicer.
Reserved
x
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