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参数资料
型号： ADV7184BSTZ
厂商： Analog Devices Inc
文件页数： 59/112页
文件大小： 0K
描述： IC DECODER VID SDTV MULTI 80LQFP
标准包装： 1
类型： 视频解码器
应用： 投影仪，录音机，安全
电压 - 电源，模拟： 3.15 V ~ 3.45 V
电压 - 电源，数字： 1.65 V ~ 2 V
安装类型： 表面贴装
封装/外壳： 80-LQFP
供应商设备封装： 80-LQFP（14x14）
包装： 托盘
ADV7184
Rev. A | Page 50 of 112
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
NFTOGDELO, NTSC Field Toggle Delay on Odd Field,
Address 0xE7 [7]
0 (default)—No delay.
1—Delays the field toggle/transition on an odd field by a line
relative to NFTOG.
NFTOGDELE, NTSC Field Toggle Delay on Even Field,
Address 0xE7 [6]
0—No delay.
1 (default)—Delays the field toggle/transition on an even field
by a line relative to NFTOG.
05
47
9-
031
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
NFTOGSIGN
ODD FIELD?
0
1
NO
YES
NFTOGDELE
ADDITIONAL
DELAY BY
1 LINE
1
0
NFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
1
0
FIELD
TOGGLE
NOT VALID FOR USER
PROGRAMMING
Figure 31. NTSC Field Toggle
NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]
0—Delays the field transition. Set for manual programming.
1 (default)—Advances the field transition. Not recommended
for user programming.
NFTOG [4:0], NTSC Field Toggle, Address 0xE7 [4:0]
The default value of NFTOG is 00011, indicating the NTSC
field toggle position.
For all NTSC/PAL field timing controls, both the F bit in the
AV code and the field signal on the FIELD/DE pin are
modified.
PVBEGDELO, PAL Vsync Begin Delay on Odd Field,
Address 0xE8 [7]
0 (default)—No delay.
1—Delays vsync going high on an odd field by a line relative to
PVBEG.
PVBEGDELE, PAL Vsync Begin Delay on Even Field,
Address 0xE8 [6]
0 (default)—No delay.
1 (default)—Delays vsync going high on an even field by a line
relative to PVBEG.
PVBEGSIGN, PAL Vsync Begin Sign, Address 0xE8 [5]
0—Delays the beginning of vsync. Set for user manual
programming.
1 (default)—Advances the beginning of vsync. Not
recommended for user programming.
PVBEG [4:0], PAL Vsync Begin, Address 0xE8 [4:0]
The default value of PVBEG is 00101, indicating the PAL vsync
begin position.
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
Table 63. Recommended User Settings for PAL (see Figure 33)
Register
Register Name
Write
0x31
Vsync Field Control 1
0x1A
0x32
Vsync Field Control 2
0x81
0x33
Vsync Field Control 3
0x84
0x34
Hsync Position 1
0x00
0x35
Hsync Position 2
0x00
0x36
Hsync Position 3
0x7D
0x37
Polarity
0xA1
0xE8
PAL V bit begin
0x41
0xE9
PAL V bit end
0x84
0xEA
PAL F bit toggle
0x06
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ADV7186BBCZ 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064
ADV7186BBCZ-RL 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064
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