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参数资料
型号： ADV7184BSTZ
厂商： Analog Devices Inc
文件页数： 54/112页
文件大小： 0K
描述： IC DECODER VID SDTV MULTI 80LQFP
标准包装： 1
类型： 视频解码器
应用： 投影仪，录音机，安全
电压 - 电源，模拟： 3.15 V ~ 3.45 V
电压 - 电源，数字： 1.65 V ~ 2 V
安装类型： 表面贴装
封装/外壳： 80-LQFP
供应商设备封装： 80-LQFP（14x14）
包装： 托盘
ADV7184
Rev. A | Page 46 of 112
Table 61. HS Timing Parameters (see Figure 26)
Characteristics
Standard
HS Begin Adjust
(HSB [10:0]) (Default)
HS End Adjust
(HSE [10:0]) (Default)
HS to Active Video
(LLC1 Clock Cycles)
(C in Figure 26) (Default)
Active Video
Samples/Line
(D in Figure 26)
Total LLC1
Clock Cycles
(E in Figure 26)
NTSC
00000000010
00000000000
272
720Y + 720C = 1440
1716
NTSC Square
Pixel
00000000010
00000000000
276
640Y + 640C = 1280
1560
PAL
00000000010
00000000000
284
720Y + 720C = 1440
1728
05
479
-0
26
E
ACTIVE
VIDEO
LLC1
PIXEL
BUS
HS
Cr
Y
FF
00
XY
80
10
80
10
80
10
FF
00
XY
Cb
Y
Cr
Y
Cb
Y
Cr
4 LLC1
D
HSB[10:0]
HSE[10:0]
C
E
D
SAV
ACTIVE VIDEO
H BLANK
EAV
Figure 26. HS Timing
HSE [10:0] HS End, Address 0x34 [2:0], Address 0x36 [7:0]
The position of this edge is controlled by placing a binary
number into HSE [10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV Code FF, 00, 00, XY (see Figure 26). HSE is set to
00000000000, which is 0 LLC1 clock cycles from Count [0].
The default value of HSE [10:0] is 000, indicating that the HS
pulse ends 0 pixels after the falling edge of HS.
For example,
To shift the HS toward active video by 20 LLC1s, add
20 LLC1s to both HSB and HSE, that is, HSB [10:0] =
[00000010110] and HSE [10:0] = [00000010100].
To shift the HS away from active video by 20 LLC1s, add
1696 LLC1s to both HSB and HSE (for NTSC), that is, HSB
[10:0] = [11010100010] and HSE [10:0] = [11010100000].
The number 1696 is derived from the NTSC total number
of pixels = 1716.
To move 20 LLC1s away from active video is equal to subtracting
20 from 1716 and adding the result in binary to both HSB [10:0]
and HSE [10:0].
PHS Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit.
0 (default)—HS is active high.
1—HS is active low.
VS and FIELD Configuration
The following controls allow the user to configure the behavior
of the VS and FIELD output pins and to generate the following
embedded AV codes:
ADV encoder-compatible signals via NEWAVMODE
PVS, PF
HVSTIM
VSBHO, VSBHE
VSEHO, VSEHE
For NTSC control
NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG [4:0]
NVENDDELO, NVENDDELE, NVENDSIGN, NVEND [4:0]
NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG [4:0]
For PAL control
PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG [4:0]
PVENDDELO, PVENDDELE, PVENDSIGN, PVEND [4:0]
PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG [4:0]
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ADV7186BBCZ 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064
ADV7186BBCZ-RL 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064
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