参数资料
| 型号： | ADV7184BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 108/112页 |
| 文件大小： | 0K |
| 描述： | IC DECODER VID SDTV MULTI 80LQFP |
| 标准包装： | 1 |
| 类型： | 视频解码器 |
| 应用： | 投影仪，录音机，安全 |
| 电压 - 电源，模拟： | 3.15 V ~ 3.45 V |
| 电压 - 电源，数字： | 1.65 V ~ 2 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
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ADV7184
Rev. A | Page 95 of 112
Bit1
Address
Register
Bit Description
7 6 5 4 3 2 1 0 Comments
Notes
0xE4
SD Saturation Cr
SD_SAT_CR [7:0]. These bits adjust the
saturation of the picture by affecting gain on
the Cr channel.
1 0 0 0 0 0 0 0 Chroma gain = 0 dB
NVBEG [4:0]. Number of lines after lCOUNT
rollover to set V high.
0 0 1 0 1 NTSC default (ITU-R BT.656)
0
Set to low when manual
programming
NVBEGSIGN.
1
Not suitable for user
programming
0
No delay
NVBEGDELE. This bit delays the V bit going
high by one line relative to NVBEG (even field).
1
Additional delay by one line
0
No delay
0xE5
NTSC V Bit Begin
NVBEGDELO. This bit delays the V bit going
high by one line relative to NVBEG (odd field). 1
Additional delay by one line
0xE6
NTSC V Bit End
NVEND [4:0]. These bits control the number
of lines after lCOUNT rollover to set V low.
0 0 1 0 0 NTSC default (ITU-R BT.656)
0
Set to low when manual
programming
NVENDSIGN.
1
Not suitable for user
programming
0
No delay
NVENDDELE. This bit delays the V bit going
low by one line relative to NVEND (even field).
1
Additional delay by one line
0
No delay
NVENDDELO. This bit delays the V bit going
low by one line relative to NVEND (odd field).
1
Additional delay by one line
NFTOG [4:0]. These bits control the number
of lines after lCOUNT rollover to toggle F signal.
0 0 0 1 1 NTSC default
0
Set to low when manual
programming
NFTOGSIGN.
1
Not suitable for user
programming
0
No delay
NFTOGDELE. This bit delays the F transition
by one line relative to NFTOG (even field).
1
Additional delay by one line
0
No delay
0xE7
NTSC F Bit Toggle
NFTOGDELO. This bit delays the F transition
by one line relative to NFTOG (odd field).
1
Additional delay by one line
PVBEG [4:0]. These bits control the number of
lines after lCOUNT rollover to set V high.
0 0 1 0 1 PAL default (ITU-R BT.656)
0
Set to low when manual
programming
PVBEGSIGN.
1
Not suitable for user
programming
0
No delay
PVBEGDELE. This bit delays the V bit going
high by one line relative to PVBEG (even field).
1
Additional delay by one line
0
No delay
0xE8
PAL V Bit Begin
PVBEGDELO. This bit delays the V bit going
high by one line relative to PVBEG (odd field).
1
Additional delay by one line
PVEND [4:0]. These bits control the number of
lines after lCOUNT rollover to set the V bit low.
1 0 1 0 0 PAL default (ITU-R BT.656)
0
Set to low when manual
programming
PVENDSIGN.
1
Not suitable for user
programming
0
No delay
PVENDDELE. This bit delays the V bit going
low by one line relative to PVEND (even field).
1
Additional delay by one line
0
No delay
0xE9
PAL V Bit End
PVENDDELO. This bit delays the V bit going
low by one line relative to PVEND (odd field).
1
Additional delay by one line
PFTOG [4:0]. These bits control the number of
lines after lCOUNT rollover to toggle the F signal.
0 0 0 1 1 PAL default (ITU-R BT.656)
0
Set to low when manual
programming
PFTOGSIGN.
1
Not suitable for user
programming
0
No delay
PFTOGDELE. This bit delays the F transition
by one line relative to PFTOG (even field).
1
Additional delay by one line
0
No delay
0xEA
PAL F Bit Toggle
PFTOGDELO. This bit delays the F transition
by one line relative to PFTOG (odd field).
1
Additional delay by one line
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| ADV7186BBCZ | 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| ADV7186BBCZ-RL | 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
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