参数资料
| 型号： | ADV7184BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 62/112页 |
| 文件大小： | 0K |
| 描述： | IC DECODER VID SDTV MULTI 80LQFP |
| 标准包装： | 1 |
| 类型： | 视频解码器 |
| 应用： | 投影仪，录音机，安全 |
| 电压 - 电源，模拟： | 3.15 V ~ 3.45 V |
| 电压 - 电源，数字： | 1.65 V ~ 2 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
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ADV7184
Rev. A | Page 53 of 112
PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5]
0—Delays the field transition. Set for manual programming.
1 (default)—Advances the field transition. Not recommended
for user programming.
PFTOG, PAL Field Toggle, Address 0xEA [4:0]
The default value of PFTOG is 00011, indicating the PAL field
toggle position.
For all NTSC/PAL field timing controls, the F bit in the AV code
and the field signal on the FIELD/DE pin are modified.
05
47
9-
036
ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
PFTOGSIGN
ODD FIELD?
0
1
NO
YES
PFTOGDELE
ADDITIONAL
DELAY BY
1 LINE
1
0
PFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
1
0
FIELD
TOGGLE
NOT VALID FOR USER
PROGRAMMING
Figure 36. PAL F Toggle
SYNC PROCESSING
The ADV7184 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits.
ENHSPLL, Enable Hsync Processor, Address 0x01 [6]
The hsync processor is designed to filter incoming hsyncs that
have been corrupted by noise; therefore, it improves the per-
formance of the ADV7184 for video signals with stable time
bases but poor SNR.
0—Disables the hsync processor.
1 (default)—Enables the hsync processor.
ENVSPROC, Enable Vsync Processor, Address 0x01 [3]
This block provides extra filtering of the detected vsyncs to
improve vertical lock.
0—Disables the vsync processor.
1 (default)—Enables the vsync processor.
VBI DATA DECODE
There are two VBI data slicers on the ADV7184. The first is
called the VBI data processor (VDP), and the second is called
the VBI System 2.
The VDP can slice both low bandwidth standards and high
bandwidth standards, such as teletext. VBI System 2 can slice
low data rate VBI standards only.
The VDP is capable of slicing multiple VBI data standards on
SD video. It decodes the VBI data on the incoming CVBS and
Y/C or YUV data. The decoded results are available as ancillary
data in the output 656 data stream. For low data rate VBI standards
such as CC/WSS/CGMS, the user can read the decoded data
bytes from I2C registers. The VBI data standards that can be
Table 64. PAL
Feature
Standard
Teletext System A or C or D
ITU-R BT.653
Teletext System B/WST
ITU-R BT.653
VPS (Video Programming System)
ETSI EN 300 231 V1.3.1
VITC (Vertical Interval Time Codes)
–
WSS (Wide-Screen Signaling)
BT.1119-1/ETSI EN 300 294
CC (Closed Captioning)
–
Table 65. NTSC
Feature
Standard
Teletext System B and D
ITU-R BT.653
Teletext System C/NABTS
ITU-R BT.653/EIA-516
VITC (Vertical Interval Time Codes)
–
CGMS (Copy Generation
Management System)
EIA-J CPR-1204/IEC 61880
Gemstar
–
CC (Closed Captioning)
EIA-608
The VBI data standard that the VDP decodes on a particular
line of incoming video has been set by default, as described in
Table 66. This can be overridden manually, and any VBI data
can be decoded on any line. The details of manual program-
VDP Default Configuration
The VDP can decode different VBI data standards on a line-to-
line basis. The various standards supported by default on different
lines of VBI are explained in Table 66.
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| ADV7186BBCZ | 功能描述:IC VIDEO DECODER 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
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