参数资料
型号: EK-V6-ML630-G-J
厂商: Xilinx Inc
文件页数: 17/65页
文件大小: 0K
描述: VIRTEX-6 HXT FPGA ML630 EVAL KIT
标准包装: 1
系列: Virtex® 6 HXT
类型: FPGA
适用于相关产品: Virtex?-6 XC6VHX565T
所含物品: 板,线缆,软件和文档
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver Specifications
GTH Transceiver DC Characteristics
Table 25: Absolute Maximum Ratings for GTH Transceivers (1)
Symbol
MGTHAVCC
MGTHAVCCRX
MGTHAVTT
MGTHAVCCPLL
V IN
V MGTREFCLK
Description
Analog supply voltage for the GTH transmitter, receiver, and common analog
circuits
Analog supply voltage for the GTH receiver circuits and common analog circuits
Analog supply voltage for the GTH transmitter termination circuits
Analog supply voltage for the GTH receiver and PLL circuits
Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage
Reference clock absolute input voltage
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
Max
1.125
1.125
1.32
1.935
1.125
1.935
Units
V
V
V
V
V
V
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 26: Recommended Operating Conditions for GTH Transceivers (1)(2)
Symbol
MGTHAVCC
MGTHAVCCRX
MGTHAVTT
MGTHAVCCPLL
Description
Analog supply voltage for the GTH transmitter, receiver, and common analog
circuits
Analog supply voltage for the GTH receiver circuits and common analog
circuits
Analog supply voltage for the GTH transmitter termination circuits
Analog supply voltage for the GTH receiver and PLL circuit
Min
1.075
1.075
1.140
1.710
Typ
1.1
1.1
1.2
1.8
Max
1.125
1.125
1.26
1.89
Units
V
V
V
V
Notes:
1.
2.
Each voltage listed requires the filter circuit described in UG371 : Virtex-6 FPGA GTH Transceivers User Guide .
Voltages are specified for the temperature range of T j = –40°C to +100°C.
Table 27: GTH Transceiver Power Supply Sequencing (1)(2)(3)
Symbol
T HAVCC2HAVCCRX
T HAVCCRX2HAVCCPLL
T HAVCCRX2HAVTT
Description
Maximum time between powering MGTHAVCC to when MGTHAVCCRX
must be powered.
Minimum time between powering MGTHAVCCRX to when
MGTHAVCCPLL can be powered.
Minimum time between powering MGTHAVCCRX to when MGTHAVTT
can be powered.
Min
0
10
10
Max
5
Units
ms
μs
μs
Notes:
1.
2.
3.
MGTHAVCCRX must be powered simultaneously or within T HAVCC2HAVCCRX of MGTHAVCC, but it must not precede MGTHAVCC.
MGTHAVCC and MGTHAVCCRX must be powered before MGTHAVCCPLL and MGTHAVTT. This minimum time is defined by
T HAVCCRX2HAVCCPLL and T HAVCCRX2HAVTT .
At any time, the condition of MGTHAVCC being present and MGTHAVCCRX not being present should not occur for more than the maximum
T HAVCC2HAVCCRX .
DS152 (v3.6) March 18, 2014
Product Specification
17
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