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参数资料
| 型号： | HY5MS5B6LF-H |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 DDR DRAM, 6.5 ns, PBGA60 |
| 封装： | 8 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, FBGA-80 |
| 文件页数： | 21/60页 |
| 文件大小： | 676K |
| 代理商： | HY5MS5B6LF-H |
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Rev 0.2 / Oct. 2004
28
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
READ / WRITE COMMAND
The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and
address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used. If autoprecharge is selected, the row being
accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open
for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.
The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble
and the last data-out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon com-
pletion of a burst, assuming no new READ commands have been initiated, the I/O's will go high-Z.
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank
and address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used.If autoprecharge is selected, the row being
accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open
for subsequent access. Input data appearing on the data bus, is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be
written to the memory; if the DM signal is registered high, the corresponding data-inputs will be ignored, and a write
will not be executed to that byte/column location. The memory controller drives the DQS during write operations. The
initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write
postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z
and any additional input data will be ignored.
READ / WRITE COMMAND
CS
A0 ~ A8
WE
CAS
RAS
Don't Care
/CLK
CLK
CKE
High-Z
CA
BA
BA0,1
Enable
Auto
Precharge
Disable
Auto
Precharge
Read Command
Operation
Write Command
Operation
A10
CS
A0 ~ A8
WE
CAS
RAS
/CLK
CLK
CKE
High-Z
CA
BA
BA0,1
A10
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5MS7B2BLFP-H | 制造商:SK Hynix Inc 功能描述: |
| HY5N50FT | 制造商:HY 制造商全称:HY ELECTRONIC CORP. 功能描述:500V / 5A N-Channel Enhancement Mode MOSFET |
| HY5N50T | 制造商:HY 制造商全称:HY ELECTRONIC CORP. 功能描述:500V / 5A N-Channel Enhancement Mode MOSFET |
| HY5P | 制造商:LEM 制造商全称:LEM 功能描述:Current Transducers HY 5 to 25-P/SP1 |
| HY5-P | 制造商:LEM Holdings SSA 功能描述:CURRENT TRANSFORMER, HY 5-P |
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