参数资料
型号: HY5MS5B6LF-H
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 16M X 16 DDR DRAM, 6.5 ns, PBGA60
封装: 8 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, FBGA-80
文件页数: 47/60页
文件大小: 676K
代理商: HY5MS5B6LF-H
Rev 0.2 / Oct. 2004
51
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
DEEP POWER-DOWN
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the
LPDDR are stopped and all memory data is lost in this mode.
All the information in the Mode Register and the Extended Mode Register is lost. Next Figure,
DEEP POWER-DOWN
COMMAND shows the DEEP POWER-DOWN command All banks must be in idle state with no activity on the data bus
prior to entering the DPD mode. While in this state, CKE must be held in a constant low state.
To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least
200 us. After 200 us a complete re-initialization routing is required following steps 4 through 11 as defined for the ini-
tialization sequence. (Page 60, 61)
DEEP POWER-DOWN COMMAND
CS
A0 ~ A9
A11, A12
WE
CAS
RAS
Don't Care
/CLK
CLK
CKE
BA0, 1
CKE_Low
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