Rev 0.2 / Oct. 2004
36
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
Write
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
Basic Write timing parameters for DQs are shown in Figure; they apply to all Write operations.
Basic Write Timing Parameters
During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the
WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of
DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS
following the last data-in element is called the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a rel-
atively wide range - from 75
% to 125% of a clock cycle. Next fig. shows the two extremes of tDQSS for a burst of 4.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain high-Z and any
aditional input data will be ignored.
/CLK
CLK
tCK
tCH
tCL
DIN
DQS
DQ,
DM
DQ,
DM
tDQSS
tDQSH
tDSH
tWPST
tWPRES
tDS
tDH
tWPRE
tDS
tDH
tWPRES
tWPRE
tDQSS
tDQSH
tWPST
tDSS
tDQSL
Don't Care
1) D
IN : Data in for column n
2) 3 subsequent elements of Data in are applied in the programmed order following D
IN
3) tDQSS : eatch rising edge of DQS must fall within the +/-25(percentage) Window of the
corresponding positive clock edge