Rev 0.2 / Oct. 2004
56
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
Extended Mode Register
The Extended Mode Register contains the specific features of self refresh opeartion of the Mobile DDR SDRAM.
The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=1 and BA0=0) and
will retain the stored information until it is reprogrammed, the device is put in Deep Power-Down mode, or the device
loses power. The Extended Mode Register should be loaded when all Banks are idle and no bursts are in progress, and
subsequent operation should only be initiated after tMRD. Violating these requirements will result in unspecified opera-
tion.
The Extended Mode Register is written by asserting low on CS, RAS, CAS, WE and high on BA0. The state of address
pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode regis-
ter. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the con-
troller must wait the specified time before initiating any subsequent operation. Violating either of these requirements
will result in unspecified operation.
This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended
mode register set must be done before any activate command after the power up sequence. Any contents of the mode
register be altered by re-programming the mode register through the execution of extended mode register set com-
mand.
PARTIAL ARRAY SELF-REFRESH (PASR)
With PASR, the self refresh may be restricted to a variable portion of the total array. The whole array (default), 1/2
array, or 1/4 array could be selected.
DRIVE STRENGTH (DS)
The drive strength could be set to full or half via address bits A5 and A6. The half drive strength is intended for lighter
loads or point-to-point environments.