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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 16/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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March 17, 1995
17
IBM
RGB524
Composite sync on HCSYNCIN may be injected onto the
Green DAC output for composite-sync-on-green. This
function is enabled by setting the SOG bit of the DAC
Operation register. If this bit is off HCSYNCIN is not
used for composite sync.
The composite sync is delayed internally to match the
pixel pipeline delay.
Since horizontal and composite sync are shared, only
one of them should be enabled at a given time. For
example, if the signal on HCSYNCIN is horizontal sync,
then the SOG bit on the DAC control register should be
off. Or, if SOG is on to inject composite sync on HCSYN-
CIN onto the green DAC output, some decision must be
made on how to handle the HSYNCOUT output (force
low, high, 3-state, or leave unconnected).
4.6
Clocking and Pipeline Delay
4.6.1
Horizontal Sync
The clocking and delay of HCSYNCIN to HSYNCOUT
depends on the DLY CNTL bit of the Sync Control regis-
ter. If this bit is set to 1, HCSYNCIN is passed directly
to HSYNCOUT without latching and without pipeline
delay matching.
If DLY CNTL is set to 0 and SOG is off (no composite
sync), then HCSYNCIN is latched on the rising edge of
LCLK and delayed internally to match the pixel pipeline
delay before being sent out on HSYNCOUT. Also, addi-
tional delay may be added with the Horizontal Position
register (see section below).
If SOG is on (composite sync) then DLY CNTL has no
effect and HCSYNCIN is passed directly to HSYNCOUT
without latching and without pipeline delay matching.
(This is not a typical use for this input, it is just a
byproduct of sharing horizontal sync with composite
sync.)
4.6.2
Vertical Sync
VSYNCIN is passed directly to VSYNCOUT without
latching and without pipeline delay matching.
4.6.3
Composite Sync
The HCSYNCIN input is always latched on the rising
edge of LCLK for use as composite sync. When enabled
with the SOG bit, it is delayed internally to match the
pipeline delay of the pixel data, and then is injected onto
the Green DAC output. As with horizontal sync, addi-
tional delay can be added with the Horizontal Sync Posi-
tion register.
4.6.4
Horizontal Position Control
Additional delay of 0 to 15 pixel clock periods may be
added to the horizontal sync and composite sync signals
with the Horizontal Sync Position register.
The intent of this additional delay is to provide a “ne
tune” control of the horizontal screen position. Typically
the incoming sync signals can only be adjusted in multi-
ples of the pixel clock. The additional delay added with
the Horizontal Position Control register adjusts the
screen position with pixel increments.
The Horizontal Position register can be used on horizon-
tal sync when DLY CNTL is set to 0 and SOG is off. The
register can be used with composite sync when SOG is
on.
4.7
Additional Sync Control
The polarity of the received HCSYNCIN input may be
inverted before it is applied to the green DAC using the
CSYN INVT bit of the Sync Control register.
The polarity may be inverted between HCSYNCIN and
HSYNCOUT using the HSYN INVT bit, and the polar-
ity may be inverted between VSYNCIN and VSYN-
COUT using the VSYN INVT bit.
The HSYNCOUT and VSYNCOUT signals may be indi-
vidually forced low, forced high, or forced to high imped-
ance using the HSYN CNTL and VSYN CNTL bits of
the Sync Control register.
As discussed in 7.3 “Clocking Power” on page 22, the
clocks to the sync delay circuits can be shut off with the
SYNC PWR bit of the Power Management register.
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