参数资料
型号: IBM37RGB524CF17A
元件分类: 显示控制器
英文描述: 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144
封装: QFP-144
文件页数: 32/72页
文件大小: 509K
代理商: IBM37RGB524CF17A
32
March 17, 1995
RGB524
IBM
Power Management
Index:
0x0005
Access:
Read/Write
Power on Value: 0x00
Bits 7 - 5
Reserved
Bit 4
SCLK PWR - SCLK Power Control
0
Normal Operation
1
Disable clocks to SCLK genera-
tor
Bit 3
DDOT PWR - DDOTCLK Power Con-
trol
0
Normal Operation
1
Disable clocks to DDOTCLK
generator
Bit 2
SYNC PWR - Sync Power Control
0
Normal Operation
1
Disable clocks to horizontal and
vertical sync circuits
Bit 1
ICLK PWR - Internal Clock Power
Control
0
Normal Operation
1
Disable all internal clocks
except those for the SCLK gen-
erator, DDOTCLK generator,
and horizontal and vertical sync
circuits.
A clock is left running to allow
microprocessor access of the
palette and cursor array, but
otherwise the palette and cur-
sor RAMs will not be clocked.
The two RAMs will retain their
contents.
Bit 0
DAC PWR - DAC Analog Power Con-
trol
0
Normal Operation
1
Disable analog power to the
DACs
DAC Operation
Index:
0x0006
Access:
Read/Write
Power on Value: 0x00
Bits 7 - 4
Reserved
Bit 3
SOG - Composite Sync-On-Green
0
Sync is disabled on Green DAC.
1
Sync is enabled on Green DAC.
Bit 2
BRB - Blank Red and Blue DACs
0
Red and Blue DACs have nor-
mal function.
1
Red and Blue DACs are always
blanked.
Bit 1
DSR - DAC Slew Rate
0
Slow - typically 14 ns
1
Fast - typically 2 ns
Bit 0
DPE - DAC blanking Pedestal
Enable
0
Blanking pedestal disabled
(0 IRE)
1
Blanking pedestal enabled
(7.5 IRE)
0
1
2
3
4
5
6
7
Reserved
SCLK DDOT
PWR PWR
SYNC ICLK DAC
PWR PWR PWR
0
1
2
3
4
5
6
7
Reserved
SOG BRB DSR
DPE
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