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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 67/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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March 17, 1995
1
IBM
RGB524
1.0
Microprocessor Access
As seen on the microprocessor bus there are eight I/O
addresses, selected by RS[2:0]. Two indirect schemes are
used to access all of the internal registers and arrays
through these eight primary I/O addresses.
The rst scheme is standard VGA, and operates when
RS[2] = 0. Of the four I/O addresses then available with
RS[1:0], only one address directly accesses a register,
the Pixel Mask. The other three addresses are used to
indirectly access the three 256x8 palettes.
The second scheme is an indexed scheme and is used to
access all of the remaining registers including the cursor
array. This scheme operates when RS[2] =1. Of the four
I/O addresses then available using RS[1:0], two are used
to load an index register (Low and High). The third
address is used to write or read the register or array
position pointed to by the index register. The fourth
address is used to directly access a register which con-
trols whether the index register automatically incre-
ments following an indexed register access.
The eight I/O addresses selected by RS[2:0] are listed in
Table 1 below:
1.1
VGA Access
1.1.1
Palette
Internally the three 256x8 palettes are accessed by the
microprocessor as a single 256x24 palette, with all 24
bits written or read in one operation.
A single Palette Address register points to 1 of 256 loca-
tions for writing or reading the 24 bits. Two different
Register Select addresses are used to access the Palette
Address register.
A write to RS[2:0] = 000 (Palette Address Write Mode)
initializes the palette logic for write operations. Subse-
quent writes to Palette Data (RS[2:0] = 001) will load
internal palette color registers and cause these register
contents to be written into the palettes.
A write to RS[2:0] = 011 (Palette Address Read Mode)
initializes the palette logic for read operations. Data
from the palettes will be loaded into internal palette
color registers. Subsequent reads from Palette Data
(RS[2:0] = 001) will read these palette color registers.
Every three accesses of Palette Data (RS[2:0] = 001) will
cause the Palette Address register to be incremented.
An increment past 0xff will “wrap around” to 0x00.
A read from either Palette Address (Write Mode) or Pal-
ette Address (Read Mode) will read the Palette Address
register. The same register is used for writing and read-
ing, thus, changing modes destroys the contents of the
previous mode’s palette address. For example, if some
reads are performed and then Palette Address (Write
mode) is written, the read address will be lost and a read
of either Palette Address (Write Mode) or Palette
Address (Read Mode) will produce the same result: the
address that was written into Palette Address (Write
Mode).
1.1.2
Palette Write
Palette writes must be initialized by writing the Palette
Address (Write Mode) register. This provides a starting
address for writes and initializes the internal circuitry
for palette write operations.
Palette writes are then performed by writing to Palette
Data in a red, green, blue... sequence. These writes will
load internal palette data registers in sequence. Imme-
diately following every third write, an internal write will
be triggered to the palette of the 24 bits contained in the
internal palette data registers, at the address contained
in the Palette Address register.
Immediately following the internal palette write trig-
gered by the third write to Palette Data, the Palette
Address register will be incremented. Thus, continuous
writes to Palette Data will load the palette, stepping
through the palette addresses in ascending order.
Table 1. I/O Addresses
RS[2:0]
Register
000
Palette Address (Write Mode)
001
Palette Data
010
Pixel Mask
011
Palette Address (Read Mode)
100
Index Low
101
Index High
110
Index Data (Indexed Registers)
111
Index Control
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