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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 66/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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March 17, 1995
63
IBM
RGB524
B.0
Relationship to Previous Generation RGB525
The RGB524 is a superset of the RGB525 and is generally upward register compatible with the RGB525. The
principal differences are these:
u
A second programmable clock generator is added for driving SYSCLK. This clock is also known as MCLK.
u
The RGB524 speed ratings are 170 and 220 MHz, whereas the RGB525 is offered in 170, 220, and 250 MHz
speeds.
u
The RGB524 uses a 144 pin QFP, whereas the RGB525 uses a 208 pin QFP.
In addition, there are some I/O and register bit differences to accommodate the smaller package size and to add the
second clock generator (PLL). The RGB524 share these same differences from the RGB525:
11. The HCSYNCIN input on the RGB524 is two separate inputs on the RGB525: HSYNCIN and CSYNCIN.
12. The BORDER/OE input on the RGB524 is two separate inputs on the RGB525: BORDER and ODD/EVEN. A
new bit, BRDR/INTL, is added to the Miscellaneous Control 2 register to select the function of this input.
13. The RGB525 has an input, “EXTCLK,” which can serve as an alternate to the REFCLK input, either as the input
reference to the PLL, or as the pixel clock. The RGB524 does not have this input.
On the RGB525 bit 4 of the PLL Control 1 register selects the reference source of the PLL, REFCLK or EXTCLK.
On the RGB524 this bit is reserved.
Bits 7 - 6 of the Miscellaneous Control 2 register select the source of the pixel clock. On the RGB525 a setting of
‘10’ will select EXTCLK. On the RGB524 this setting selects REFCLK.
14. The RGB525 pixel clock generator resets to the “off ” condition and must be programmed before it is enabled. This
allows a wide range of incoming REFCLK frequencies.
The RGB524 pixel clock generator is the same, but the new SYSCLK PLL powers up enabled, with default pro-
gramming values. REFCLK is shared between the two PLLs. This may restrict the REFCLK frequency, depend-
ing on how the generated SYSCLK is used at reset time.
15. System Clock Control (index 0x0008), System PLL Reference Divider (index 0x0015), and System PLL VCO
Divider (index 0x0016) registers are added for controlling and programming the SYSCLK PLL.
16. The Miscellaneous Clock Control register has a bit added, SCLK INVT, that inverts the out-going SCLK. This is
intended as an aid for meeting tight timings at the card level.
17. Two external frequency selects FS[3], FS[2] are eliminated. This restricts the external pixel frequency selection
to four sets of values. Using internal selection, 16 values (direct programming) or 8 values (M/N programming)
can still be chosen, the same as for the RGB525.
18. The ID register is changed to a value of “0x02”.
19. In the Miscellaneous Control 3 register, the SWAP WORD bit is deleted. This RGB525 feature is not available on
the RGB524.
20. The RGB525 pixel PLL requires two external resistors RPLLI and REXT. The two PLLs on the RGB524 do not
require these resistors. Each PLL still requires external loop lter components.
21. The RGB525 TESTMODE input is TESTMODE on the RGB524. TESTMODE now has an internal pull-down
resistor, so it may be left unconnected at the card level.
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