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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 39/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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38
March 17, 1995
RGB524
IBM
10.2.3
Pixel Clock Frequency Selection
Pixel PLL Control 1
Index:
0x0010
Access:
Read/Write
Power on Value: 0x00
Bits 7 - 3
Reserved
Bits 2 - 0
EXT/INT
Determines the source and selection
for the Pixel PLL programming reg-
isters.
000 External FS[1:0] inputs
One of the F0 - F3 registers is
selected with external signals
FS[1:0]. The selected register
provides the Pixel PLL VCO
divider value. The Fixed Pixel
PLL Reference Divider register
is used to pre-scale the PLL ref-
erence clock.
001 External FS[1:0] inputs (4 value
M/N programming)
Four pairs of registers M0/N0,
M1/N1, M2/N2, M3/N3 are
selected with external signals
FS[1:0] to provide the VCO
divider/reference divider inputs
to the Pixel PLL.
The Fixed PLL Reference
Divider register is not used.
0
1
2
3
4
5
6
7
EXT/INT
Reserved
010 Pixel PLL Control 2 register
bits [3:0] (16 value direct pro-
gramming)
One of the F0 - F15 registers is
selected with Pixel PLL Control
2 register bits [3:0]. The
selected register provides the
Pixel PLL VCO divider value.
The Fixed Pixel PLL Reference
Divider register is used to pres-
cale the Pixel PLL reference
clock.
011 Pixel PLL Control 2 register
bits [2:0] (8 value M/N direct
programming)
Eight pairs of registers M0/N0,
M1/N1, M2/N2, M3/N3, M4/N4,
M5/N5, M6/N6, M7/N7 are
selected with Pixel PLL Control
2 register bits [2:0] to provide
the VCO divider/reference
divider inputs to the Pixel PLL.
The Fixed Pixel PLL Reference
Divider register is not used.
Pixel PLL Control 2 register bit
3 has no effect.
100 Reserved
101 Reserved
110 Reserved
111 Reserved
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