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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 17/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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18
March 17, 1995
RGB524
IBM
4.8
24 Bit Packed Pixel Control
The 24 bit packed pixel format requires special consider-
ation. In this mode the pixel data at the beginning of a
line must be aligned on an eight pixel boundary as
shown in Figure 2, “24 BPP Packed Pixel Input from
VRAM” on page 12. These eight pixels correspond to
three 64-bit pixel port loads or three SCLK cycles. In
order to keep pixel data and control signals properly
aligned, all control signals (BLANK, BORDER/OE and
HCSYNCIN) are required to change in increments of
eight pixels (3 SCLKS). When either BLANK or BOR-
DER/OE changes to indicate the beginning of an active
display line, it is assumed that the pixel data which
begins that line is aligned on the proper eight pixel
boundary.
5.0
Cursor Operation
The cursor is a 32x32 or 64x64 pixel pattern that is
overlaid on the display pixels just before presentation to
the DACs. The cursor size, 32x32 or 64x64 is set with
the CURS SIZE bit of the Cursor Control register.
Pixel columns are numbered left to right starting with 0.
Pixel rows are numbered top to bottom starting with 0.
5.1
Cursor Enable
The cursor is enabled when the CURSOR MODE bits of
the Cursor Control register are not 00. When enabled,
the cursor will display if it has not been moved off-
screen. If disabled (CURSOR MODE = 00), the cursor
will not be displayed.
The cursor may be used with either pixel port (VGA or
PIX), with any of the pixel formats (VGA, 4, 8, 15/16, 24,
32 BPP), and with indirect or direct color.
5.2
Cursor Array
The cursor image is stored in the Cursor Array. The
array is organized 1024x8 (1024 bytes). It is accessed as
Indexed Data using index addresses 0x0100 through
0x04ff.
Each pixel of the cursor uses 2 bits, thus 4 cursor pixels
are stored in each byte of the array. The entire array is
used to contain the 64x64 cursor image (4 pixels/byte
×
1024 bytes = 4096 pixels = 64x64).
For the 32x32 cursor only 256 bytes are required (4 pix-
els/byte
× 256 bytes = 1024 pixels = 32x32.) The cursor
array is divided into four contiguous slots to allow the
storage of four cursor images. The SMLC SLOT bits of
the Cursor Control register are used to select one of the
four slots for display. The SMLC SLOT bits have no
effect when the cursor size is 64 x 6 4.
Storage of the cursor within the array starts with the
top row. For the 64x64 cursor the rst 16 bytes hold row
0, the next 16 bytes hold row 1, and so on, starting with
the rst byte in the array at index address 0x0100.
For the 32x32 cursor the rst 8 bytes hold row 0, the
next 8 bytes hold row 1, and so on, starting with the rst
byte in a slot (index addresses 0x0100, 0x0200, 0x0300
or 0x0400).
Within a row the pixels are stored left to right in groups
of four. The rst byte holds pixels 0, 1, 2, 3, the next byte
holds pixels 4, 5, 6, 7, and so on.
Within a byte the four pixels may be stored right to left
or left to right, depending on the PIX ORDR bit of the
Cursor Control register. If PIX ORDR = 0 the pixels are
stored right to left (3, 2, 1, 0); if PIX ORDR = 1 the pixels
are stored left to right (0, 1, 2, 3).
5.2.1
Cursor Array Access
Cursor Array writes and reads are synchronized with
the internal pixel clock, so the pixel clock must be run-
ning for microprocessor accesses to be valid. If this con-
dition is met, the cursor array may be written or read at
any time.
Microprocessor read accesses of the cursor array may
disturb the cursor image if it is being displayed at that
time. However, no more than one cursor pixel will be
disturbed per cursor read access. Microprocessor write
accesses of the cursor array will not disturb the cursor.
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