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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 30/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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30
March 17, 1995
RGB524
IBM
Miscellaneous Control 3
Index:
0x0072
Access:
Read/Write
Power on Value: 0x00
Bit 7
SWAP RB - Swap Red and Blue pixel
components. In 16, 24, and 32 BPP,
this bit causes the red and blue com-
ponents of the pixels to be swapped.
In indirect mode, the swapping takes
place before the Palette.
0
Normal operation.
1
Swap Red and Blue components
of the pixel. This bit only has an
effect in 16, 24, and 32 BPP.
Bits 6 - 2
Reserved
Bit 1
SWAP NIB - Swap nibbles within
bytes. Used with 4 BPP.
0
Use high nibble (e.g.,
PIX[07:04]) for rst pixel, use
low nibble (e.g., PIX[03:00]) for
next pixel.
1
Use low nibble (e.g., PIX[03:00])
for rst pixel, use high nibble
(e.g., PIX[07:04]) for next pixel.
The same nibble order is applied to
each of the incoming bytes. This bit
has no effect if the pixel format is not
4 BPP.
Bit 0
Reserved
This register has no effect when the VGA port is
selected.
0
1
2
3
4
5
6
7
Reserved
SWAP
RB
RSVD
SWAP
NIB
Miscellaneous Clock Control
Index:
0x0002
Access:
Read/Write
Power on Value: 0x00
Bit 7
DDOT DSAB - DDOTCLK driver dis-
able
DDOTCLK driver enabled
0
DDOTCLK driver enabled
1
DDOTCLK driver disabled (3-
stated)
Bit 6
SCLK DSAB - SCLK driver disable
0
SCLK driver enabled
1
SCLK driver disabled (3-stated)
Bit 5
B24P DDOT - Selects which clock is
driven on DDOTCLK when 24 Bit
Packed Pixel format is selected.
0
Use divided Pixel PLL output
under control of DDOT DIV
bits.
1
Output the same signal as
SCLK.
When a format other than 24 BPP
Packed is selected, the B24P DDOT
bit has no effect and the divided
Pixel PLL output is used.
Bit 4
SCLK INVT - Inverts the SCLK out-
put.
Bits 3 - 1
DDOT DIV - DDOTCLK divide fac-
tor. Species the divide factor applied
to the internal Pixel PLL output to
produce the DDOTCLK output sig-
nal.
000 Pixel PLL out/1
001 Pixel PLL out/2
010 Pixel PLL out/4
011 Pixel PLL out/8
100 Pixel PLL out/16
101 Reserved
110 Reserved
111 Reserved
Bit 0
PPLL ENAB - Pixel PLL Enable
0
Pixel PLL programming
disabled.
1
Pixel PLL programming
enabled.
0
1
2
3
4
5
6
7
DDOT
DSAB DSAB DDOT
SCLK B24P SCLK
DDOT DIV
PPLL
ENAB
INVT
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