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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 21/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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22
March 17, 1995
RGB524
IBM
7.0
Power Management
The following registers are used to control power dissi-
pation:
u
Power Management (index 0x0005)
u
Miscellaneous Clock Control (index 0x0002)
u
Sync Control (index 0x0003)
u
Miscellaneous Control 1 (index 0x0070)
7.1
DAC Power
The analog portion of the DACs can be shut down with
the DAC PWR bit of the Power Management register. A
small amount of current (approximately 100
A) will
continue to be drawn through the VREFIN input. This
can be eliminated if the voltage on VREFIN is reduced
to 0 V.
7.2
Driver Power
The power dissipated by the logic output signals can be
reduced by 3-stating the drivers. This is done for the
SCLK driver by setting the SCLK DSAB bit of the Mis-
cellaneous Clock Control register. The DDOTCLK driver
can also be 3-stated by setting the DDOT DSAB bit of
the Miscellaneous Clock Control register. HSYNCOUT
and VSYNCOUT are 3-stated by setting HSYN CNTL
and VSYN CNTL bits of the Sync Control register. The
SENSE output is 3-stated by setting the SENS DSAB
bit of the Miscellaneous Control 1 register.
The remaining drivers are the microprocessor D[7:0] sig-
nals. These are normally 3-stated and will not dissipate
power unless a microprocessor read is performed.
7.3
Clocking Power
Most of the digital logic power dissipation occurs as a
result of clocking. The ICLK PWR, SCLK PWR, DDOT
PWR, and SYNC PWR bits of the Power Management
register are used to inhibit the digital logic clocking.
The ICLK PWR bit, when set, inhibits all internal clock-
ing except for the following:
u
The PLL.
u
The palette arrays and the cursor array control
logic. The clocks to the internal logic are left
running because this is required for
microprocessor access.
u
SCLK and DDOTCLK - The circuitry that
generates these clocks is left running in case
external components need to run off these
clocks.
u
The horizontal and vertical sync delay circuits.
These circuits are left running to allow sync
signals to propagate to the display monitor.
When the ICLK PWR bit is set the DAC outputs will
remain stuck at whatever was last clocked into the
DACs, unless the DACs are shut down with DAC PWR.
The SCLK PWR bit may be set to disable the clocking to
the SCLK generator. The resultant static SCLK output
may be left at either the low or high state. As noted
above, the SCLK output may be 3-stated with the SCLK
DSAB bit of the Miscellaneous Clock Control register.
The DDOT PWR bit may be set to disable the clocking to
the DDOTCLK generator. The resultant static DDOT-
CLK output may be left at either the low or high state.
As noted above, the DDOTCLK output may be 3-stated
with the DDOT DSAB bit of the Miscellaneous Clock
Control register.
The SYNC PWR bit may be set to disable the clocking to
the horizontal and vertical sync circuits. These outputs
may be left at either the low or high state. (But note that
the outputs can be forced high or low or 3-stated with
the HSYN CNTL and VSYN CNTL bits of the Sync Con-
trol register.)
The starting and stopping of clocks with the SCLK
PWR, DDOT PWR, and SYNC PWR bits is asynchro-
nous. Thus, “chopped” pulses may be produced on the
SCLK, DDOTCLK, HSYNCOUT and VSYNCOUT out-
puts when these bits are changed.
Similarly, changing the ICLK PWR bit can disturb the
stopping and starting of the internal clocks such that
the display is disturbed for a frame. It is recommended
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