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8
March 17, 1995
RGB524
IBM
2.10
Direct Programming
Use the following steps to calculate the values used with
direct programming:
1.
the given programming value into the PLL
Reference Divider register (System PLL Reference
Divider for the SYSCLK PLL, Fixed Pixel PLL
Reference Divider for the pixel PLL). If the
incoming REFCLK frequency does not appear in
this table, then the direct programming method
cannot be used.
2.
to determine the values to write into the VCO
Divider register (System PLL VCO Divider for the
SYSCLK PLL, F0 - F15 for the pixel PLL). First,
pick the row of the table whose frequency range
covers the frequency of interest. This will determine
the value of the DF bits to write. Next, use the given
equation to calculate the value of the VCO DIV
BITS. Write these two values together to the
appropriate register.
The generated pixel clock frequency is designated in
this table as VF, for Video Frequency. Note that
within each range the desired VF frequency must
lie on a given step value (e.g., with DF = 11 a
frequency of 159 MHz is invalid because it does not
lie on a 2 MHz step; but either 158 MHz or 160 MHz
is valid).
Table 5. Direct Programming Reference Divider Values
REFCLK (MHz)
Fixed PLL Reference Divider
Register Value
4
0x0002
6
0x0003
8
0x0004
10
0x0005
12
0x0006
14
0x0007
16
0x0008
18
0x0009
20
0x000a
22
0x000b
24
0x000c
26
0x000d
28
0x000e
30
0x000f
32
0x0010
34
0x0011
36
0x0012
38
0x0013
40
0x0014
42
0x0015
44
0x0016
46
0x0017
48
0x0018
50
0x0019
52
0x001a
54
0x001b
56
0x001c
58
0x001d
60
0x001e
62
0x001f
Table 6. PLL Direct Programming Equations
DF
VCO Divide
Count
Frequency Range Step (MHz)
00
(4 x VF) - 65
16.25 - 32 MHz
0.25
01
(2 x VF) - 65
32.5 - 64 MHz
0.5
10
VF - 65
65.0 - 128 MHz
1.0
11
(VF / 2) - 65
130.0 - 220 MHz
2.0
VF = Desired Video Frequency