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参数资料
| 型号： | IBM37RGB524CF17A |
| 元件分类： | 显示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP144 |
| 封装： | QFP-144 |
| 文件页数： | 72/72页 |
| 文件大小： | 509K |
| 代理商： | IBM37RGB524CF17A |
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March 17, 1995
3
IBM
RGB524
1.1.7
Pixel Mask
The pixel mask is an 8-bit register addressed with
RS[2:0] = 010. It can be accessed at any time without
disturbing a palette write or read sequence.
Accesses to the pixel mask are asynchronous to the pixel
clock. Temporary color disturbances can be expected if
the mask is changed while displaying pixels through the
palette.
1.2
Indexed Access
The cursor array and a number of control registers are
addressed with an internal 11-bit index register. The
microprocessor accesses this as Index High (RS[2:0] =
101) and Index Low (RS[2:0] = 100).
A write or read to Index Data (RS[2:0] = 110) actually
writes or reads the register/cursor array location
addressed by the Index register.
Following a write or read of Index Data, the index regis-
ter will increment if the INDX CNTL bit is set. The
Index Control register (RS[2:0] = 111) contains this bit.
To allow for future expansion, wraparound from 0x07ff
to 0x0000 is not supported.
In general, access of Index Low, Index High, Index Con-
trol, or any of the Indexed registers is independent of
the palette access and will not disturb a palette write or
read sequence. However, as described above the PADR
RFMT bit in Miscellaneous Control 1, the COL RES bit
in Miscellaneous Control 2, and the 6BIT ACC bit in
Palette Control all affect palette access.
Also, as described above, the pixel clock must be running
for valid access of the palette, and the pixel clock is
affected by a number of indexed registers.
1.2.1
Cursor Array
In general, the indexed registers may be written or read
at any time, using the address held in Index High and
Index Low. This address may be set by writing to Index
High or Index Low, or the value may result from the
auto-increment action of a previous access.
However, as described in section 5.2.3 Cursor Array
Reads on page 19, to access the cursor array a write to
Index High or Index Low must be performed rst. That
is, the cursor array cannot be accessed by auto-incre-
ment from address 0x00ff to 0x0100.
Also, as with the palette, the pixel clock must be run-
ning to access the cursor array.
2.0
Clocking
2.1
Clock Generators
There are two on-board clock generators: pixel clock and
system clock (SYSCLK). Each clock generator uses a
separate programmable phase locked loop (PLL).
The pixel clock generator provides the fundamental
“dot” timings; it serves generally as the clock both for
internal chip clocking and for on-card CRT timings.
The system clock generator is provided for the conve-
nience of the graphics subsystem design. No internal
use is made of this clock; the clock generator simply
drives the SYSCLK output of the chip.
2.2
PLL Input
2.2.1
REFCLK
The REFCLK input is a reference clock that the PLLs
use in conjunction with programming registers to pro-
duce a wide variety of frequencies.
In general, REFCLK can be any frequency from 2 MHz
through 100 MHz.
As discussed below, following a reset the PLL driving
the SYSCLK output is enabled with the start-up fre-
quency:
SYSCLK frequency = (33/16)
× REFCLK frequency
If it is important to have a particular frequency on
SYSCLK following a reset, then the REFCLK frequency
must be chosen that produces the desired SYSCLK fre-
quency.
Also, when the “direct programming” method is used to
program the PLL frequencies (see below), then REFCLK
must lie on a 2 MHz boundary in the range of 4 MHz
through 62 MHz (4 MHz, 6 MHz, 8 MHz,... 62 MHz).
2.3
SYSCLK PLL Output
The system clock PLL drives the SYSCLK output. Two
bits in the System Clock Control register affect this out-
put. Bit 6, SYSC DSAB, is used to 3-state the driver. Bit
1, SYSC SRC, is used to bypass the SYSCLK PLL (the
incoming REFCLK is steered to the SYSCLK output).
The supported frequency range for SYSCLK is 16.25
MHz to 100 MHz.
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相关代理商/技术参数 |
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