参数资料
型号: M37902FCCHP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 110/143页
文件大小: 1148K
代理商: M37902FCCHP
69
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Transmission
clock
TEj
1/fi
× (n + 1) × 2
1/fi
× (n + 1) × 2
TIj
CTSj
Write in transmit buffer register
D0 D1 D2 D3 D4 D5 D6 D7
D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0
Transmit register
←Transmit buffer register
Stopped because TEj = “0”
CLKj
TENDj
TXDj
TXEPTYj
Fig. 70 Clock synchronous serial I/O timing
Interrupt request at completion of reception
When the RIk flag changes from “0” to “1”, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to “1”.
The timing when this interrupt request bit is to be set to “1” can be
selected from the following:
Each reception
When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UART re-
ceive interrupt mode select bit) is cleared to “0”, the interrupt request
bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt re-
quest bit is set to “1” only when an error occurs. (In the clock syn-
chronous serial communication, only when an overrun error occurs,
the interrupt request bit is set to “1”.)
Polarity of transfer clock
In the clock synchronous serial communication, by bit 6 of the UARTj
transmit/receive control register 0 (CPL), the polarity of a transfer
clock can be selected.
As shown in Figure 71, when bit 6 = “0”, the polarity is as follows:
In transmission, transmit data is output at the falling edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at “H” level.
When bit 6 = “1”, the polarity is as follows:
In transmission, transmit data is output at the rising edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at “L” level.
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