参数资料
型号: M37902FCCHP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 74/143页
文件大小: 1148K
代理商: M37902FCCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
36
Fig. 25 Bit configuration of processor mode register 1
Notes 1: This bit is valid to the external area except for chip select areas (area CSi), and the bus cycle of area CSi is independent
of this bit’s contents.
The bus cycle of area CSi is selected by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016,
8216, 8416, 8616; bit 3 at addresses 8116, 8316, 8516, 8716).
2: After reset, this bit’s contents can be switched only once. During the software execution, be sure not to switch this bit’s contents.
3: In the single-chip mode, these bits’ functions are disabled regardless of these bits’ contents.
4: While VSS level voltage is applied to pin MD0, each of these bits is “0” at reset. While VCC level voltage is applied
to pin MD0, on the other hand, each of these bits is “1” at reset.
5: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”.
After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer.
6: The program which switches this bit’s contents must be assigned to the internal area.
7: In the microprocessor mode, this bit is invalid.
When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to “0”.
7
6
543
2
1
0
Processor mode register 1
External bus cycle select bit 1 (Note 1)
See Figure 18.
RDY input select bit (Notes 3 to 5)
0 : RDY input is disabled. (P30 functions as a programmable I/O port pin.)
1 : RDY input is enabled. (P30 functions as pin RDY.)
ALE output select bit (Notes 3 and 4)
0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.)
1 : ALE output is enabled. (P40 functions as pin ALE.)
Direct page register switch bit (Note 2)
0 : Only DPR0 is used.
1 : DPR0 to DPR3 are used.
Recovery cycle insert select bit (Notes 3 and 4)
0 : No recovery cycle is inserted at access to the external area.
1 : Recovery cycle is inserted at access to the external area.
Address
5F16
HOLD input, HLDA output select bit (Notes 3 to 5)
0 : HOLD input and HLDA output are disabled.
(P43 and P42 function as programmable I/O port pins.)
1 : HOLD input and HLDA output are enabled.
(P43 and P42 function as pins HOLD and HLDA, respectively.)
Recovery-cycle-insert number select bit (Note 6)
0 : 1 cycle
1 : 2 cycles
Internal ROM bus cycle select bit (Note 7)
0 : 3
φ
1 : 2
φ
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