参数资料
型号: M37902FCCHP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 116/143页
文件大小: 1148K
代理商: M37902FCCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
74
Table 13. Selection methods of CTS/RTS function
CTSi/RTSi
separate select bit
0
1
Functions
CTS0
RTS0
P80
Pin P81/CTS0/CLK0
P81 or CLK0
CTS0 (Notes 2 and 3)
P81 or CLK0
Pin P84/CTS1/RTS1
Pin P85/CTS1/CLK1
Notes 1: When using the CTS0/RTS0 pin, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0”.
2: When using the CTS function, be sure to clear the corresponding bit of the port P8 direction register to “0”.
3: When CTSi and RTSi has been separated, the CLKi pin cannot be used. Therefore, in the clock synchronous serial communication, CTSi and RTSi
cannot be separated. Also, when CTSi and RTSi are separated in UART mode, be sure to select an internal clock.
CTS/RTS
function select bit
CTS/RTS
enable bit
0
1
0
1
Pin P80/CTS0/RTS0 (Note 1)
CTS1
RTS1
P84
P85 or CLK1
CTS1 (Notes 2 and 3)
P85 or CLK1
: It may be “0” or “1”.
Fig. 76 Bit configuration of serial I/O pin control register
CTS0/RTS0 separate select bit
0 : CTS0/RTS0 are used together.
1 : CTS0/RTS0 are separated.
CTS1/RTS1 separate select bit
0 : CTS1/RTS1 are used together.
1 : CTS1/RTS1 are separated.
TxD0/P83 switch bit
0 : Functions as TxD0.
1 : Functions as P83.
TxD1/P87 switch bit
0 : Functions as TxD1.
1 : Functions as P87.
76543210
Serial I/O pin control register
Address
AC16
At reset
X016
Receive
Receive is enabled when bit 2 (REi flag) of UARTi transmit/receive
control register 1 is set to “1.” As shown in Figure 75, the frequency
divider circuit (1/16) at the receiving side begin to work when a start
bit arrives and the data is received.
________
If RTSi output is selected by setting bit 2 of UARTi transmit/receive
________
control register 0 to “1”, the RTSi output is “H” when the REi flag is
________
“0”. When the REi flag changes to “1”, the RTSi output goes “L” to
inform the receiver that reception has become enabled. When the
________
receive operation starts, the RTSi output automatically becomes “H”.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 66. At this
point, the contents of the receive register is transferred to the receive
buffer register and bit 3 (Rli flag) of UARTi transmit/receive control
register 1 is set to “1.” In other words, the RIi flag indicates that the
receive buffer register contains data when it is set to “1.” At this time,
when the low-order byte of the UARTk receive buffer register is read
________
out, RTSi output goes back to “L” to indicate that the register is ready
to receive the next data.
Bit 4 (OERi flag) of UARTi transmit/receive control register 1 is set to
“1” when the next data is transferred from the receive register to the
receive buffer register while the RIi flag is “1”, in other words, when
an overrun error occurs. If the OERi flag is “1”, it indicates that the
next data has been transferred to the receive buffer register before
the contents of the receive buffer register has been read.
Bit 5 (FERi flag) is set to “1” when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set to “1” when a parity error occurs.
Bit 7 (SUMi flag) is set to “1” when either the OERi flag, FERi flag, or
the PERi flag is set to “1.” Therefore, the SUMi flag can be used to
determine whether there is an error.
The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is
performed while transferring the contents of the receive register to
the receive buffer register.
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