参数资料
型号: M37902FCCHP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 127/143页
文件大小: 1148K
代理商: M37902FCCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
84
1/16
Watchdog timer
frequency select bit
“FFF16” is set.
Writing to watchdog
timer register
STP instruction
Watchdog timer
interrupt request
Wf32
Wf512
Watchdog timer
f2
Wait mode
Access to
external area
HLDA
1/16
1
0
Watchdog timer register: address 6016
Watchdog timer frequency select register: bit 0 at address 6116
Watchdog timer clock source select bits at STP state termination: bits 6, 7 at address 6116
When the most significant bit of the watchdog timer becomes “0”, this signal will be generated.
Note: During the stop mode and until the stop mode is terminated, setting for disabling the
watchdog timer is ignored.
RESET
Disables watchdog
timer (Note).
fX16
fX32
fX64
fX128
Watchdog timer clock source select
bits at STP state termination
Stop mode
Divided f(XIN)
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 87 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf32, which is obtained by dividing
the peripheral devices’ clock f2 by 16; or clock Wf512, which is ob-
tained by doing it by 256. Bit 0 of the watchdog timer frequency se-
lect register (watchdog timer frequency select bit) shown in Figure 88
selects which clock is to be counted.
Wf512 is selected when this bit 0 is “0”, and Wf32 is selected when bit
0 is “1”. Bit 0 is cleared to “0” after reset.
FFF16 is set in the watchdog timer when “L” level voltage is applied
to pin RESET, STP instruction is executed, data is written to the
watchdog timer register (address 6016), or the most significant bit of
the watchdog timer becomes “0”.
After FFF16 is set in the watchdog timer, when the watchdog timer
counts Wf32 or Wf512 by 2048 counts, the most significant bit of
watchdog timer becomes “0”, the watchdog timer interrupt request
bit is set to “1”, and FFF16 is set again in the watchdog timer.
In program coding, make sure that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“0”. If this routine is not executed owing to unexpected program ex-
ecution or others, the most significant bit of the watchdog timer be-
Fig. 87 Block diagram of watchdog timer
Fig. 88 Bit configuration of watchdog timer frequency select register
76543210
Watchdog timer frequency select register
Watchdog timer frequency select bit
0 : W f512
1 : W f32
Watchdog timer clock source select bits at STP
state termination
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
76543210
Address
6116
comes “0” and an interrupt is generated.
The microcomputer can generate a reset pulse by writing “1” to bit 6
(software reset bit) of processor mode register 0 in an interrupt rou-
tine and can be restarted.
The watchdog timer can also be used to return from the STP state,
where a clock has stopped its operation owing to the STP instruction
execution. For details, refer to the sections on the clock generating
circuit and standby function.
The watchdog timer stops its operation in the following cases, and at
this time, input to the watchdog timer is disabled:
When the external area is accessed in the hold state
In the wait mode
In the stop mode
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