参数资料
型号: M37902FCCHP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 52/143页
文件大小: 1148K
代理商: M37902FCCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
MITSUBISHI MICROCOMPUTERS
16
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BANK
In order to effectively use the integrated hardware on the chip, this
CPU core uses an address generating method with a 24-bit address
split into high-order 8 bits and low-order 16 bits. In other words, the
64 Kbytes specified by the low-order 16 bits are one unit (referred to
as “bank”), and the address space is divided into 256 banks (016 to
FF16) specified by the high-order 8 bits.
In the program area on the address space, the bank is specified by
the program bank register (PG), and the address in the bank is
specified by the program counter (PC).
As for each bank boundary, when an overflow has occurred in PC,
the contents of PG are incremented by 1. When a borrow has oc-
curred in PC, the contents of PG are decremented by 1. Under the
normal conditions, therefore, programming without concern for the
bank boundaries is possible. Furthermore, as for the data area on
the address space, the bank is specified by the data bank register
(DT), and the address in the bank is specified by the operation result
by using the various addressing modes (Note).
Note: Some addressing modes directly specify a bank.
DIRECT PAGE
The internal memory and control registers for internal peripheral de-
vices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The
direct page and direct addressing modes have been provided for the
effective access to bank 016. In the 7900 Series, two types of direct
addressing modes are available: the conventional direct addressing
mode which uses only DPR0, as in the 7700 Series, and the ex-
panded direct addressing mode, which uses up to 4 direct page reg-
isters as selected by the user. The addressing mode is selected
according to the contents of bit 1 of the processor mode register 1.
This bit 1 is cleared to “0” at reset. (In other words, the conventional
direct addressing mode is selected.) However, once this bit 1 has
been set to “1” by software, this bit cannot be cleared to “0” again,
except by reset. That is to say, when one of these two direct address-
ing modes has been selected just after reset, the selected address-
ing mode cannot be switched to another one while the program is
running.
s Conventional direct addressing mode
The direct page area consists of 256-byte space. Its bank address is
“0016”, and the base address of its low-order 16-bit address is speci-
fied by the contents of the direct page register 0 (DPR0). In this con-
ventional direct addressing modes, a value (1 byte) just after an
instruction code is regarded as an offset value for the DPR0 con-
tents, and the CPU accesses each address in the direct page area.
s Expanded direct addressing mode
The direct page area consists of four 64-byte spaces. Their bank
address is “0016”, and the four base addresses of their low-order 16-
bit addresses are respectively specified by the contents of four direct
page registers. In this expanded direct addressing mode, a value (1
byte) just after an instruction code is regarded as follows:
High-order 2 bits: regarded as a selection field for DPR0 to DPR3.
Low-order 6 bits: regarded as an offset value for the selected direct
page register.
Then, the CPU accesses each address in each direct page area:
Refer to “7900 Series Software Manual” for details concerning the
various addressing modes which use the direct page area.
Instruction Set
The CPU core of the 7900 Series has an expanded instruction set
based on the existing 7700/7751 Series’ CPU core. In addition, its
source code (mnemonic) has the complete upper compatibility with
the 7700 Series instruction set.
For details concerning addressing modes and instruction set, refer to
“7900 Series Software Manual”.
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