参数资料
型号: M37902FCCHP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数: 48/143页
文件大小: 1148K
代理商: M37902FCCHP
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.9
Page
Error
Correction
(9/11)
Page 92,
Table 15,
Note
Note: Be sure that system clock fsys does not exceed 26
MHz. f(XIN) means the frequency of the input clock
from pin XIN (fXIN).
Note: The PLL multiplication ratio must be set so that the
frequency of the PLL output clock (fPLL) must be in
the range from 10 MHz to 26 MHz. f(XIN) means the
frequency of the input clock from pin XIN (fXIN). After
reset, the PLL multiplication ratio select bits are
allowed to be changed only once.
Page 98,
Right column,
Line 8
Page 98,
Right column,
Line 10
the ladder network of the A-D converter will
the resistor ladder network of the A-D converter will
pin VREF to the ladder network, and the power dissipation
pin VREF to the resistor ladder network, and the power
dissipation
5
Page 96,
Left column,
Line 7
the oscillation circuit and PLL circuit have been
restarted
the oscillation circuit has been restarted
5
M37902F8CGP, M37902F8CHP : block configuration of
internal flash memory
(Deleted)
5
Fig. 106. M37902FJCGP, M37902FJCHP : block confi-
guration of internal flash memory
Fig. 106. M37902FJCHP : block configuration of inter-
nal flash memory
Page 101,
Fig. 106
5
Fig. 108. M37902FCCGP, M37902FCCHP : block con-
figuration of internal flash memory
Fig. 107. M37902FCCHP : block configuration of inter-
nal flash memory
Page 102,
Fig. 107
5
M37902FECGP, M37902FECHP : block configuration
of internal flash memory
(Deleted)
Fig. 110. M37902FGCGP, M37902FGCHP : block con-
figuration of internal flash memory
Fig. 108. M37902FGCHP : block configuration of inter-
nal flash memory
Page 102,
Fig. 108
5
M37902FHCGP, M37902FHCHP : block configuration
of internal flash memory
(Deleted)
5
Page 103,
Right column,
Lines 15 to 17
area if the user uses the flash memory serial I/O mode.
Note that, when the boot ROM area is read
area if the user uses the flash memory serial I/O mode.
Addresses FFB016 to FFBF16 are the reserved area for
the serial programmer. Therefore, when the user uses
the flash memory serial I/O mode, do not program to this
area.
Note that, when the boot ROM area is read
5
Page 106,
Right column,
After line 13
program the user ROM area.
After reset removal, be sure not to change the status at
pins MD0 and MD1.
5
Pin connection of M37902FxCGP in flash memory
serial I/O mode
(Deleted)
Page 106,
Fig. 114,
Notes 4
5
4: Valid only clear to “0”.
4: Valid only clear to “0”. This bit 3 must be controll-
ed with bit 1 = “1”.
Page 107,
Left column,
Lines 16 to 20
5
command consists of 8-bit units must be written only
to an even address; therefore, any data written to an odd
address will be invalid.
The write state
command consisting of 8 bits must be written to an
even address; therefore, any command written to an odd
address will be invalid. Since the write data at the 2nd
cycle of a programming command consists of 16 bits, this
data must be written to even and odd addresses.
The write state
Page 107,
Right column,
After line 24
5
request occurrence.
request occurrence. In the CPU reprogramming mode,
be sure not to use the STP and WIT instructions.
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