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参数资料
型号： M37902FCCHP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封装： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件页数： 136/143页
文件大小： 1148K
代理商： M37902FCCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
92
CLOCK GENERATING CIRCUIT
Figure 98 shows the block diagram of the clock generating circuit.
The clock generating circuit consists of the clock oscillation circuit,
PLL frequency multiplier (PLL circuit), system clock switch circuit,
peripheral devices’ clock switch circuit, clock divider, standby control
circuit, etc. As control registers for the clock generating circuit, also,
the clock control register (address BC16), particular function select
register 0 (address 6216) are provided. (See Figures 99 and 100.)
As shown in Figure 98, clocks used in the CPU, BIU, peripheral de-
vices, watchdog timer (in other words, clocks
φCPU, φBIU, f1 to f4096,
Wf32, Wf512) are made from system clock fsys. System clock fsys can
be selected between fXIN (in other words, a clock input from pin XIN)
and fPLL (in other words, an output clock generated by the PLL cir-
cuit). By setting the clock
φ1 output select bit (bit 7 of the processor
mode register 0) to “1”, also, system clock fsys can be output from
port pin P41, as clock
φ1.
The PLL circuit’s operation, system clock (fsys) selection, and divide
ratio selection for peripheral devices’ clocks (f1 to f4096) are con-
trolled by the clock control register. The following describes about
these control.
Bit 1 of the clock control register (the PLL circuit operation enable bit)
selects the PLL circuit’s operation (stopped/active). When this bit is
set to “1”, pin VCONT will becomes valid, and the PLL circuit will oper-
ate. At reset, the PLL circuit operation enable bit becomes “1”. (In this
case, the PLL circuit operates.) When not using the PLL circuit, be
sure to clear the PLL circuit operation enable bit to “0” (stopped). At
the STP instruction execution or while the flash memory parallel I/O
mode is set, the PLL circuit stops its operation, and pin VCONT is in-
valid, regardless of this bit 1’s status.
Bits 2 and 3 of the clock control register (the PLL multiplication ratio
select bits) select the ratio of fPLL/fXIN. The PLL multiplication ratio
must be set so that the frequency of the PLL output clock (fPLL) must
be in the range from 10 MHz to 26 MHz. At reset, the PLL multiplica-
tion ratio select bits become “0,1” ( 2). The change of the multipli-
cation ratio must be performed while input clock fXIN is set as system
clock. (In this case, bit 5 of the clock control register = “0”.) After that,
be sure to wait that the operation-stabilizing time of the PLL circuit
has passed, and switch the system clock to the PLL output clock
(fPLL). (In other words, set bit 5 to “1”.) Note that, after reset, the PLL
multiplication ratio select bits are allowed to be changed only once.
Bit 5 of the clock control register is the system clock select bit, and
fXIN is selected as the system clock when bit 5 = “0”. On the other
hand, when bit 5 = “1”, the PLL output clock (fPLL) is selected. At re-
set, the system clock select bit becomes “0”. When selecting fPLL, be
sure that the PLL circuit’s operation has been stabilized properly, and
then, set the system clock select bit to “1”. Also, when the PLL circuit
operation enable bit is cleared to “0” (the PLL circuit is stopped.), the
system clock select bit will automatically be cleared to “0”. Note that
a value of “1” cannot be written to the system clock select bit while
the PLL circuit operation enable bit =“0”.
Table 15 lists the fsys selection.
Bits 6 and 7 of the clock control register are the peripheral devices’
clock select bits 0, 1, and these bits select the multiplication ratio of
(f1 to f4096)/(fsys).
Table 16 lists the internal peripheral devices’ operation clock fre-
quency. At reset, these bits become “0, 0”.
Table 15. fsys selection
Table 16. Internal peripheral devices’ operation clock frequency
10 ( 3)
01 ( 2)
System clock fsys
11 ( 4)
fXIN
fPLL
Clock source
Frequency (Note)
Note: The PLL multiplication ratio must be set so that the frequency of the PLL output clock (fPLL) must be in the range from 10 MHz to 26 MHz.
f(XIN) means the frequency of the input clock from pin XIN (fXIN). After reset, the PLL multiplication ratio select bits are allowed to be
changed only once.
PLL circuit operation enable bit
(Bit 1)
System clock select bit
(Bit 5)
1
0
1
f(XIN)
f(XIN) 2
f(XIN) 3
f(XIN) 4
PLL multiplication ratio select bits
(Bits 3, 2) (Note)
fsys/16
fsys/2
Peripheral devices’ clock select bits 1, 0 (bits 7, 6)
fsys/64
fsys
fsys/8
fsys/32
1 0
1 1
Note: When selecting the peripheral devices’ clock select bits 1, 0 = “012”, be sure that system clock fsys does not exceed 13 MHz.
Internal peripheral devices’
operation clock
f1
f16
fsys/2
fsys/4
fsys/32
fsys/128
0 1 (Note)
0 0
f2
f64
f512
f4096
fsys
fsys/512
fsys/4096
fsys/256
fsys/2048
fsys/1024
fsys/8192
Do not select.
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