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参数资料
| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 1/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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Intel StrataFlash Wireless Memory
System (LV18/LV30 SCSP)
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
Product Features
The Intel StrataFlash
Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family
with Asynchronous Static RAM device offers a high performance code and large embedded data
segment plus RAM combination in a common package with electrical QUAD+ ballout on 0.13
m ETOX VIII flash technology. The code segment flash die features 1.8 V low-power
operations with flexible, multi-partition, dual operation Read-While-Write / Read-While-Erase,
asynchronous and synchronous burst reads at 54 MHz. The data segment flash die features 1.8 V
low-power operations optimized for cost sensitive asynchronous data applications. This device
integrates up to three flash dies, two PSRAM dies, and one SRAM die in a low-profile package
compatible with other SCSP families using the QUAD+ ballout package.
■
Device Architecture
— Code and data segment: 128- and 256-
Mbit density; PSRAM: 32- and 64-Mbit
density; SRAM: 8 Mbit density.
— Top or bottom parameter configuration.
— Asymmetrical blocking structure.
— 16-KWord parameter blocks (Top or
Bottom); 64-K Word main blocks.
— Zero-latency block locking.
— Absolute write protection with block
lock down using F-WP#.
■
Device Voltage
— Core: VCC = 1.8 V (typ).
—I/O: VCCQ = 1.8 V or 3.0 V (typ).
■
Device Concurrent Operations (3 Dies)
— Buffered EFP: 600 KB per second.
— Erase Performance: 384 KB per second
(main blocks).
■
Device Packaging
— 88 balls (8 x 10 active ball matrix).
— Area: 8x10mmor8x 11 mm.
— Height: 1.0 mm to 1.4 mm.
■
Quality and Reliability
— Extended Temp: –25
°Cto+85 °C.
— Minimum 100 K flash block erase cycle.
■
xRAM Performance
— PSRAM at 1.8 V I/O : 85 ns initial
access, 30 ns async page reads; 65 ns
initial access, 18 ns async page.
— SRAM at 1.8 or 3.0 V I/O: 70 ns initial
access.
■
Flash Performance
— Code Segment at 1.8 V I/O: 85 ns initial
access; 25 ns async page read; 14 ns
sync reads (tCHQV); 54 MHz CLK.
— Data Segment at 1.8 V I/O: 170 ns initial
access; 55 ns async page read.
■
Flash Architecture
— Hardware Read-While-Write/Erase.
— 8-Mbit or 16-Mbit Multi-Partition.
— 2-Kbit One-Time Programmable (OTP)
Protection Register.
— Software Read-While-Write/Erase.
— Single Full-Die Partition size.
■
Flash Software
—Intel FDI, Intel PSM, and Intel
VFM.
— Common Flash Interface (CFI).
— Basic/Extended Command Set.
253852-002
December 2003
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
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