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参数资料
| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 11/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
19
R-OE#
Input
RAM OUTPUT ENABLE:
Low-true input.
R-OE# low enables the selected RAM output buffers. R-OE# high disables the RAM
output buffers, and places the selected RAM outputs in High-Z.
R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an
RFU on flash-only stacked combinations.
F-WE#
Input
FLASH WRITE ENABLE:
Low-true input.
F-WE# controls writes to the selected flash die. Address and data are latched on the
rising edge of F-WE#.
R-WE#
Input
RAM WRITE ENABLE:
Low-true input.
R-WE#controlswritestothe selected RAMdie.
R-WE# is available on stacked combinations with PSRAM or SRAM die and is an
RFU on flash-only stacked combinations.
CLK
Input
CLOCK:
Synchronizes the flash die with the system bus clock in synchronous read
mode and increments the internal address generator.
During synchronous read operations, addresses are latched on the rising edge of
ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, addresses are latched on the rising edge ADV#, or are
continuously flow-through when ADV# is kept asserted.
WAIT
Output
WAIT:
Output signal.
Indicates data is valid in synchronous array or non-array sync flash reads.
Configuration Register bit 10 (CR.10, WT) determines its polarity when asserted.
With F-CE# and F-OE# at VIL,WAIT’s active outputis VOL or VOH.WAITishigh-Zif
F-CE# or F-OE# is VIH.
In synchronous array or non-array flash read modes, WAIT indicates invalid data
when asserted and valid data when deasserted.
In asynchronous flash page read, and all flash write modes, WAIT is deasserted.
F-WP#
Input
FLASH WRITE PROTECT:
Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected flash
die.
F-WP# low enables the lock-down mechanism where locked down blocks cannot
be unlocked with software commands.
F-WP# high disables the lock-down mechanism, allowing locked down blocks to
be unlocked with software commands.
ADV#
Input
ADDRESS VALID:
Low-true input.
During synchronous flash read operations, addresses are latched on the rising edge
of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous flash read operations, addresses are latched on the rising edge of
ADV#, or are continuously flow-through when ADV# is kept asserted.
R-UB#
R-LB#
Input
RAM UPPER / LOWER BYTE ENABLES:
Low-true input.
During RAM read and write cycles, R-UB# low enables the RAM high order bytes on
D[15:8], and R-LB# low enables the RAM low-order bytes on D[7:0].
R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die
and are RFU on flash-only stacked combinations.
F-RST#
Input
FLASH RESET:
Low-true input.
F-RST# low initializes flash internal circuitry and disables flash operations. F-RST#
high enables flash operation. Exit from reset places the flash in asynchronous read
array mode.
Table 2.
Signal Descriptions (Sheet 2 of 3)
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