768-Mbit LVQ Family with Asynchronous Static RAM
48
Datasheet
18.3
PSRAM Low-Power Mode
In addition to the regular Standby mode with a full density data hold, Low-Power Mode performs
partial density data refresh or zero density data refresh.
The Low-Power Mode allows the user to turn off sections of the PSRAM die to save refresh
current. The PSRAM die is divided into four sections allowing certain sections to be refreshed with
P-Mode at a logical-low.
In regular Standby mode, both P-CS# and P-Mode are logical-high. But in Low-Power Mode, P-
Mode is a logical-low. In Low-Power Mode, if 0-Mbit setting is set as the density, it is necessary to
perform initialization the same way as after applying power in order to return to normal operation
on page 45 for timing charts. When the density has been to set to 16 Mbit, 8 Mbit, or 4 Mbit in
Low-Power Mode, it is not necessary to perform initialization to return to normal operation from
Figure 22. PSRAM Low-Power Mode Entry/Exit (16-, 8-, 4-, 0-Mbit) Waveform
tMHCL1/tMHCL2
tCHML
Low Power Mode
(Partial Array Refresh/Zero Refresh)
P-Mode
P-CS#
Table 21. PSRAM Low-Power Mode Entry/Exit Timing
Parameter
Description
MIN
MAX
Unit
tCHML
Low-Power Mode entry, P-CS# high-level to P-Mode# low-level
0
–
ns
tMHCL1
1
Low-Power Mode (16-, 8-, 4-Mbit hold) exit to normal operation, P-Mode
high-level to P-CS# low-level
30
–
ns
tMHCL2
2
Low-Power Mode (0-Mbit data hold) exit to normal operation, P-Mode
high-level to P-CS# low-level
200
–
s
NOTES:
1. tMHCL1 is the time it takes to return to normal operation from Low-Power Mode (data hold: 16-, 8-, 4-Mbit).
2. tMHCL2 is the time it takes to return to normal operation from Low-Power Mode (0-Mbit data hold).