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参数资料
| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 13/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
20
Datasheet
P-Mode,
P-CRE
Input
P-Mode (PSRAM Mode):
Low-true input.
P-MODE is used to program the configuration register, and enter/exit Low-Power
Mode of PSRAM die.
P-Mode is available on stacked combinations with asynchronous-only PSRAM die.
P-CRE (PSRAM configuration register enable):
High-true input.
P-CRE is high, write operations load the refresh control register or bus control
register.
P-CRE is applicable only on combinations with synchronous PSRAM die.
P-Mode, P-CRE s RFU on stacked combinations without PSRAM die.
F-VPP,
F-VPEN
Power
FLASH PROGRAM AND ERASE POWER:
Valid F-VPP voltageonthisball enables
flash program/erase operations.
Flash memory array contents cannot be altered when F-VPP(F-VPEN)< VPPLK
(VPENLK). Erase / program operations at invalid F-VPP (F-VPEN) voltages should not
be attempted. Refer to flash discrete product datasheet for additional details.
F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP
products.
F[2:1]-VCC
Power
FLASH LOGIC POWER:
F1-VCC supplies power to the core logic of flash die #1;
F2-VCC supplies power to the core logic of flash die #2 and flash die #3. Write
operations are inhibited when F-VCC <VLKO. Device operations at invalid F-VCC
voltages should not be attempted.
F2-VCC is available on stacked combinations with two or three flash dies, and is an
RFU on stacked combinations with only one flash die.
S-VCC
Power
SRAM POWER SUPPLY:
Supplies power for SRAM operations.
S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked
combinations without SRAM die.
P-VCC
Power
PSRAM POWER SUPPLY:
Supplies power for PSRAM operations.
P-VCC is available on stacked combinations with PSRAM die, and is RFU on stacked
combinations without PSRAM die.
VCCQ
Power
DEVICE I/O POWER:
Supply power for the device input and output buffers.
VSS
Power
DEVICE GROUND:
Connect to system ground. Do not float any VSS connection.
RFU
RESERVED for FUTURE USE:
Reserved for future device functionality/
enhancements. Contact Intel regarding the use of balls designated RFU.
DU
Don’t Use:
Do not connect to any other signal, or power supply; must be left floating.
Table 2.
Signal Descriptions (Sheet 3 of 3)
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