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| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 29/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
35
9.0
Design Guide: Operation Overview
9.1
Bus Operations
With F-CE# low and F-RST# high, the flash dies are enabled for normal operations. The flash
device internally decodes upper address inputs to determine the accessed partition or block.
In an asynchronous read operation, addresses are latched when ADV# transition from VIL to VIH,
or continuously flows through if ADV# is held low. In synchronous-burst mode, addresses are
latched by the rising edge of ADV# or the next valid CLK edge when ADV# is low.
Table 13, “Flash + PSRAM + SRAM Bus Operations” summarizes the bus operations and voltage
levels that must be applied to individual flash die in each mode
Note:
Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares
basic asynchronous read and write operations unless otherwise specified.
Table 13. Flash + PSRAM + SRAM Bus Operations (Sheet 1 of 2)
D
evi
ce
Mo
d
e
F-
R
S
T#
F1
-C
E
#
F2
-C
E
#
F-
O
E
#
F-
WE
#
WA
IT
AD
V#
F-
V
P
S-
C
S
1
#
S-
C
S
2
P-
M
o
de
P-
C
S
#
R-
OE#
R-
W
E
#
R-
UB#
,
R-
L
B
#
D[
1
5
:0
]
No
te
s
Fl
as
hD
ie
#1
(c
o
d
e
)
Synchronous
Array and Non-
Array Read
HL
H
Active
L
X
H
X
H
XX
X
Flash
DOUT
1,2,3,4
,5,6,9
Asynchronous
Read
H
L
H
L
H
Deasserted
L
X
H
XX
H
XX
X
Flash
DOUT
1,2,3,4
,5,6,9
Write
H
L
H
L
Deasserted
L
VPP1
or
VPP2
H
XX
H
XX
X
Flash
DIN
3,4,6
Output Disable
H
L
H
High-Z
X
High-Z
Any xSRAM mode allowed
Flash
High-Z
4
Standby
H
X
High-Z
X
High-Z
Flash
High-Z
4
Reset
L
XXXX
High-Z
X
High-Z
Flash
High-Z
4
Fl
as
h
D
ie
#
2
(d
at
a
)
Synchronous
Array and Non-
Array Read
H
L
H
Deasserted
L
X
HX
X
H
X
Flash
Die #2
DOUT
1,2,3,4
,5,6,9
Async Read
H
L
H
Deasserted
L
X
HX
X
H
X
Flash
Die #2
DOUT
1,2,3,4
,5,6,9
Write
H
L
H
L
Deasserted
L
Vpp1
or
Vpp2
HX
X
H
X
Flash
Die #2
DOUT
3,4,6
Output Disable
H
L
H
High-Z
X
High-Z
Any xSRAM mode allowed
Flash#
2 High-
Z
4
Standby
H
X
High-Z
X
High-Z
Flash
#2
High-Z
4
Reset
L
XXXX
High-Z
X
High-Z
Flash
#2
High-Z
4
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