参数资料
型号: PF38F3352LLZDQ0
厂商: INTEL CORP
元件分类: 存储器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封装: 11 X 13 MM, SCSP-88
文件页数: 21/54页
文件大小: 966K
代理商: PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
28
Datasheet
W8
tWR
Write Recovery
0
ns
4
W9
tBW
R-UB#, R-LB# Setup to R-WE# (S-CS1#)
Going High
60
ns
NOTES:
1. A write occurs during the S-CS1# and R-WE# asserted overlap (tWP). The write begins with the latest
transition of S-CS1# and R-WE# going low (R-UB# and/or R-LB# already asserted). The write ends at the
earliest transition of S-CS1# or R-WE# going high.
2. tCW is measured from S-CS1# going low to the end of a write.
3. tAS is measured from address valid to the beginning of a write.
4. tWR is measured from the end of a write to the address change; tWR applied in case a write ends as S-
CS1# or R-WE# going high.
Table 9.
SRAM AC Write Specifications (Sheet 2 of 2)
Figure 10. SRAM Write Waveform
High Z
Data In
Address Stable
Device
Address Selection
Standby
ADDRESSES
V
IH
V
IL
V
IH
V
IL
S-CS1#
V
IH
V
IL
V
OH
V
OL
V
IH
R-OE#
R-WE#
DATA
R- UB#, R- LB#
High Z
V
IH
V
IL
W1
W8
S-CS2
V
IH
V
IL
V
IH
W9
W6
W5
W2
W3
W4
W7
Table 10. SRAM Data Retention Timing
Parameter
Description
MIN
MAX
Unit
tSDR
Data Retention Set-up Time
0
ns
tRDR
Data Retention Recovery Time
70
ns
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