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参数资料
| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 24/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
30
Datasheet
7.5
PSRAM AC Read Specifications
Table 11. PSRAM AC Read Specifications
#
Symbol
Parameter
P-VCC = 1.80 V to 1.95 V P-VCC = 2.7 V to 3.1 V
Unit
Note
MIN
MAX
MIN
MAX
Read Cycle
R1
tRC
Read Cycle Time
85*
–65
–
ns
5
R2
tAA
Address access time
–
85*
–65
ns
5
R3
tCO
P-CS# Low to Output Valid
–
85*
–65
ns
5
R4
tOE
R-OE# Low to Output Valid
–
65
–
45
ns
R5
tBA
R-UB#, R-LB# Low to Output Valid
–
85*
–65
ns
5
R6
tLZ
P-CS# Low to Output in Low-Z
10
–
10
–
ns
R7
tOLZ
R-OE# Low to Output in Low-Z
5
–
5
–
ns
R8
tHZ
P-CS# High to Output in High-Z
–
25
–
25
ns
R9
tOHZ
R-OE#HightoOutput inHigh-Z
–
25
–
25
ns
R10
tOH
Output Hold from Address change
5
–
5
–
ns
R11
tBLZ
R-UB#, R-LB# Low to Output in Low-Z
5
–
5
–
ns
R12
tBHZ
R-UB#, R-LB#HightoOutput inHigh-Z
–
25
–
25
ns
R13
tASO
Address set to R-OE# low-level
0
–
0
–
ns
1
R14
tOHAH
R-OE# high-level to address hold
-5
–
-5
–
ns
R15
tCHAH
P-CS# high-level to address hold
0
–
0
–
ns
1
R16
tBHAH
R-LB#, R-UB# high-level to address hold
0
–
0
–
ns
1,2
R17
tCLOL
P-CS# low-level to R-OE# low-level
0
10,000
0
10,000
ns
3
R18
tOLCH
R-OE# low-level to P-CS# high-level
60
–
45
–
ns
R19
tCP
P-CS# high-level pulse width
10
–
10
–
ns
R20
tBP
R-UB#, R-LB# high-level pulse width
10
–
10
–
ns
R21
tOP
R-OE# high-level pulse width
–
10,000
–
10,000
ns
3
Page Mode
PR1
tPC
Page Cycle Time
30
–
18
–
ns
4
PR2
tPA
Page Mode Address Access Time
–
30
–
18
ns
NOTES:
1. When R13
2. R16 is specified from when both R-LB# and R-UB# become high-level.
3. R17and R21 (MAX) are applied while P-CS# is being hold at low-level.
5. * 32-Mbit 1.8V PSRAM initial read access timing specifications changed from 85 ns to 88 ns.
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