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参数资料
| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 32/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
38
Datasheet
17.0
Dual Operation Considerations
17.1
Product Configurations and Memory Partitioning
By default, the first flash die is the first code segment flash die, a fast, eXecute-In-Place (XIP)
solution ideal for an instruction fetch application. This portion is the user-selected parameter
configuration option, made up of either a 128-Mbit flash die or a 256-Mbit flash die, each
containing one parameter partition and several main partitions. The parameter partition contains
four 16-KWord parameter blocks and seven 64-KWord main blocks; all main partitions consist of
eight 64-KWord main blocks.
The large, embedded data segment is a single partition asynchronous page-mode read device that
can be made up of multiple dies with densities of 128-Mbit or 256-Mbit. The single partition is
made up of four 16-Kword parameter blocks and 64-Kword main blocks. The data segment flash
die parameter configuration will always be the opposite of the code segment flash die parameter
configuration. See Table 14onpage 39 for examples of configuration options.
The code and embedded data portions of the LVQ device are both asymmetrical in blocking. Each
memory block features zero-latency block locking. Data integrity is protected even further with the
optional use of F-VPP and F-WP# to implement block lock down.
The user has the choice of selecting either a top or a bottom parameter partition configuration for
the code segment flash die. Depending on the choice of configuration, the data segment flash die in
the LVQ device will be parametrically opposed. For instance, if the user selects top parameter
configuration for the code segment flash die, the data segment flash die in the package will be
configured as bottom parameter configuration, and vice-versa. This ensures the largest number of
contiguous main block addresses for software efficiency.
The xRAM segment can consist of up to two Pseudo-SRAM (PSRAM) dies and one SRAM die
with the following possible densities:
The first PSRAM die can have a density of 64-Mbit or 128-Mbit.
The second PSRAM die can have a density of 64-Mbit or 32-Mbit.
The SRAM die has a density of 8-Mbit.
For the code segment, the 128-Mbit flash die has an 8-Mbit partition block and the 256-Mbit flash
die has a 16-Mbit partition block. The minimum code + data density combination for the LV18/
LV30 family is 384 Mbit.
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