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| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 40/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
45
18.0
PSRAM Operations
18.1
PSRAM Power-up Sequence and Initialization
The PSRAM functionality and reliability are independent of the power-up slew rate of the core P-
VCC. Any power-up slew rate is possible under use conditions.
The following power-up sequence and operation should be used before starting normal operation.
The PSRAM power-up sequence is represented in Figure 20. At power-up, hold P-Mode low for
the period of tVHMH and transition P-CS# from low to high before transitioning P-Mode to a logical
high. P-CS# and P-Mode must be held high for the period of tMHCL before normal PSRAM
operation is possible once the power up sequence is complete.
18.2
PSRAM Mode Register
The PSRAM die has an internal register that helps control the Low-Power Mode of the PSRAM.
This register is called the Mode Register. A fraction of the PSRAM array can be enabled for refresh
by setting the Mode Register. Available fixed, partial-refresh fraction densities are 16 Mbit, 8 Mbit,
4 Mbit and 0 Mbit for all density options. Once the refresh density has been set in the Mode
Register, these settings are retained until they are set again while applying the power supply.
However, the Mode Register setting will become undefined if the power is turned off; therefore, it
is important that the Mode Register is set again after power application.
Figure 20. Timing Waveform for PSRAM Power-Up Sequence
Table 19. PSRAM Initialization Timing
Parameter
Symbol
MIN
MAX
Unit
Power application to P-Mode low-level hold
tVHMH
50
–
s
P-CS# high-level to P-Mode high-level
tCHMH
0–
ns
Following power application, P-Mode high-
level holdtoP-CS# low-level
tMHCL
200
–
s
tVHMH
tMHCL
tCHMH
Initi alization
Vcc (MIN)
Normal Operation
P-CS#
P-Mode
P-Vcc
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