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参数资料
| 型号： | PF38F3352LLZDQ0 |
| 厂商： | INTEL CORP |
| 元件分类： | 存储器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封装： | 11 X 13 MM, SCSP-88 |
| 文件页数： | 30/54页 |
| 文件大小： | 966K |
| 代理商： | PF38F3352LLZDQ0 |
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768-Mbit LVQ Family with Asynchronous Static RAM
36
Datasheet
9.2
Flash Device Commands and Command Definitions
Refer to the Intel StrataFlash
Wireless Memory System (LV18/LV30 SCSP), 1024-Mbit LV Family
Datasheet (order number 253854) for complete descriptions of flash modes and commands, for
command bus-cycle definitions, and for flowcharts that illustrate operational routines.
Note:
Each flash die within the 768-Mbit LVQ Family with Asynchronous Static RAM device shares
basic asynchronous read and write operations unless otherwise specified.
P
S
RAM
(#
1
o
r
#
2
)
Read
X
H
L
X
High-Z
X
H
L
H
L
PSRAM
DOUT
1,3
Write
X
H
L
X
High-Z
X
H
L
H
L
PSRAM
DIN
3
Output Disable
Any Flash or SRAM mode allowed
HHH
L
H
X
PSRAM
High-Z
4
Standby
HHHH
X
PSRAM
High-Z
4
Low-Power
Mode
H
HL
XXX
X
PSRAM
High-Z
4
S
RAM
E
n
a
b
le
d
Read
X
High-Z
X
L
H
X
H
L
H
L
SRAM
DOUT
1,3,8
Write
X
High-Z
X
L
H
X
H
L
SRAM
DIN
3,8
Output Disable
Any Flash or PSRAM mode allowed
L
H
X
HHH
X
SRAM
High-Z
3,8
Standby
H
X
H
X
SRAM
High-Z
4,8
Data Retention
Same as SRAM Standby
SRAM
High-Z
7,8
NOTES:
1. WAIT is active during sync burst read when F-CE# and OE# are asserted. WAIT is High-Z if F-CE# or OE# is deasserted.
2. FX-CE# is F1-CE# for Flash #1, F2-CE# for Flash #2, and F3-CE# for Flash #3. FX-OE# is F1-OE# for Flash #1, and F2-
OE# for Flash #2.
3. For Flash, FX-OE# and F-WE# should never be asserted simultaneously. For PSRAM or SRAM, R-OE# and R-WE# should
never be asserted simultaneously.
4. X can be VIL or VIH for inputs and VPP1, VPP2,VPPLK or VPPH for F-Vpp.
5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].
6. Refer to Intel Strataflash Wireless Memory System Datasheet for valid DIN during flash writes.
7. The SRAM can be placed into data retention mode by lowering S-VCC to the VDR limit when in standby mode.
8. P-Mode is high if PSRAM is in Standby. P-Mode is low if PSRAM is in Low-Power Mode. Please see Section 18.0, “PSRAM
Operations” on page 45 for more details on Standby and Low-Power Mode.
9. Data segment flash only operates in asynchronous mode, CLK is ignored and WAIT is deasserted.
Table 13. Flash + PSRAM + SRAM Bus Operations (Sheet 2 of 2)
D
e
vi
ce
Mo
d
e
F-R
S
T#
F1
-C
E#
F2
-C
E#
F-O
E
#
F-W
E
#
WA
IT
ADV#
F-V
P
S-CS
1
#
S-CS
2
P-M
o
de
P-CS
#
R-OE#
R-W
E
#
R-UB#
,
R-L
B
#
D[1
5
:0
]
No
te
s
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