参数资料
型号: PF38F3352LLZDQ0
厂商: INTEL CORP
元件分类: 存储器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封装: 11 X 13 MM, SCSP-88
文件页数: 41/54页
文件大小: 966K
代理商: PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
46
Datasheet
18.2.1
PSRAM Mode Register Setting
Since the initial value of the PSRAM Mode Register at power application is undefined, the Mode
Register must be set after initialization at power application. When setting the density of partial
refresh, data is not guaranteed before entering the Low-Power Mode. (This is the same for reset.)
However, since Low-Power Mode is not entered unless P-Mode is a logical low, when partial
refresh is not used, it is not necessary to set the Mode Register. Also, when using page read without
using partial refresh, it is not necessary to set the Mode Register.
The PSRAM Mode Register setting can be entered by successively writing two specific data after
two continuous reads of the highest address. The Mode Register setting is a continuous four-cycle
operation: two read cycles and two writes cycles. See Table 20 for setting PSRAM Mode Register
steps in setting the Mode Register. Figure 18 on page 34 illustrates the timing waveform.
Table 20. Setting PSRAM Mode Register Command Sequence
Command
Sequence
1st Bus Cycle
(Read Cycle)
2nd Bus Cycle
(Read Cycle)
3rd Bus Cycle
(Write Cycle)
4th Bus Cycle
(Write Cycle)
Partial refresh
density
Address
Data
Address
Data
Address
Data
Address
Data
16-Mbit
Highest
Address
_
Highest
Address
_
Highest
Address
0x00
Highest
Address
0x04
8-Mbit
Highest
Address
_
Highest
Address
_
Highest
Address
0x00
Highest
Address
0x05
4-Mbit
Highest
Address
_
Highest
Address
_
Highest
Address
0x00
Highest
Address
0x06
0-Mbit
Highest
Address
_
Highest
Address
_
Highest
Address
0x00
Highest
Address
0x07
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