768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
9
2.0
Functional Overview
This section provides an overview of the code and embedded data segment features and
capabilities of the 768-Mbit LVQ Family with Asynchronous Static RAM device.
2.1
Device Description
The 768-Mbit LVQ Family with Asynchronous Static RAM device incorporates flash dies used as
code segment flash memory and large embedded data segment flash memory, along with xRAM
for a high performance, cost-effective high density memory system solution. This stacked device
uses the latest Intel StrataFlash Wireless Memory System on 0.13 m ETOX VIII process
technology.
The code segment is a high performance, multi-partition, synchronous burst-mode Read-While-
Write (RWW) or Read-While-Erase (RWE) flash memory die, while the large, embedded data
segment is a cost efficient, single-partition, asynchronous flash memory die.
The package for this device is available in a QUAD+ ballout, which supports flash only or flash +
PSRAM and/or SRAM stacked memory combinations. The SCSP in a QUAD+ ballout with a 0.8
mm ball pitch, 8x10 active ball matrix supports a memory subsystem up to 66 MHz on a x16-bit
diagram.
Figure 1. LV18/LV30 device family block diagram
LVQ Family
F-WP#
Code Segment
Optional Flash Die # 3
(128- or 256-Mbit)
FlashDie#1
(128- or 256-Mbit)
Data Segment
Optional FlashDie#3
(128- or 256-Mbit)
FlashDie#2
(128- or 256-Mbit)
F1-CE#
F2-CE#
F3-CE#
F-RST#
F[2:1]-OE#
F-WE#
WAIT
ADV#
CLK
A[MAX:MIN]
D[15:0]
S-CS2
R-WE#
R-OE#
P-MODE
/ P-CRE
P[2:1]-CS#
S-CS1#
R-LB#
P-VCC
S-VCC
R-UB#
VSS
xRAM Segment
Die # 2
64-or128-Mbit
PSRAM
Die # 1
32- 64- or 128-
Mbit PSRAM
Die#3
8-Mbit SRAM
F-VPP
F-VCC
VCCQ