参数资料
型号: PF38F3352LLZDQ0
厂商: INTEL CORP
元件分类: 存储器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封装: 11 X 13 MM, SCSP-88
文件页数: 2/54页
文件大小: 966K
代理商: PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
10
Datasheet
The 768-Mbit LVQ Family with Asynchronous Static RAM device consists of a 1.8 V flash
memory device with 1.8 V and 3.0 V I/O options. As shown in Figure 1, “LV18/LV30 device
family block diagram” on page 9, the device is available with a minimum of one flash die each per
code segment and data segment (flash die # 1 and flash die #2). An optional third flash die is
available for either the code or data segment. See Table 1, “768 Mbit LVQ Family Matrix” on
page 10 for possible combinations.
Designed for low-voltage systems, the LVQ supports read operations with F-VCC at 1.8V,and
erase and program operations with F-Vpp at 1.8 V. Buffered Enhanced Factory Programming
(Buffered-EFP) provides the fastest flash array programming performance, with elevated F-VPP at
9.0 V to increase factory throughput. With F-VPP at 1.8 V, F-Vcc and F-Vcc can be tied together
for a simple, ultra-low-power design. In addition to voltage flexibility, a dedicated F-VPP
connection provides complete data protection when F-Vpp
VPPLK.
The Intel StrataFlash
Wireless Memory System provides data security through its individual zero-
latency block lock capability. Each memory block can be unlocked, locked, or locked-down by
hardware or software control.
Individualized F-CE# control allows the user to manage which flash die is asserted, furthering the
flexibility of power management while controlling data integrity per segment with F-WP#. The
F[2:1]-OE# in LVQ products with QUAD+ ballout are common internally
Table 1.
768 Mbit LVQ Family Matrix
Line Item
Flash Components
RAM Components
Package Size
Notes
1.8 V I/O
256L18 + 256L18
None
8x11x1.2
1
256L18 + 256V18
64PS + 64PS
11x13x1.4
1
3.0 V I/O
256L30 + 256V30
None
8x11x1.2
1
NOTES:
1. Available in Top or Bottom Configurations.
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